diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-01 08:24:52 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-02 16:59:44 +0000 |
| commit | 37c332782a90c2a3f1543ece585ac305d6c610de (patch) | |
| tree | 52ad2233e35c69fe9f249dd10c2b295934440b62 /src/mainboard/google/brya/variants | |
| parent | a91eb90d44bccd0a785b4659ebbeae5da08eea83 (diff) | |
mb/google/brya: Fix a few mistakes in brya0 overridetree
1) Both SAR sensors had a UID of `2`, making them indistinguishable
2) No `device` underneath max98357a `chip`
Change-Id: Icf586229532819a7779652cbee73755b036dfbdc
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51145
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/brya0/overridetree.cb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 030d19e6fa..b70f156b51 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -73,7 +73,7 @@ chip soc/intel/alderlake register "desc" = ""SAR1 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" register "speed" = "I2C_SPEED_FAST" - register "uid" = "2" + register "uid" = "1" register "reg_gnrl_ctrl0" = "0x16" register "reg_gnrl_ctrl1" = "0x21" register "reg_afe_ctrl0" = "0x00" @@ -183,6 +183,7 @@ chip soc/intel/alderlake register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" register "sdmode_delay" = "5" + device generic 0 on end end end device ref gspi1 on |