diff options
| author | Wisley Chen <wisley.chen@quanta.corp-partner.google.com> | 2021-09-13 10:08:03 +0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-22 02:35:33 +0000 |
| commit | 04613e9b942098af65768f63fef1b41e6597c50f (patch) | |
| tree | e4a02667144d27aea9fb8b1d7b06bef6f0dc8b83 /src/mainboard/google/brya/variants | |
| parent | 16ae682cb93764016c6b31ef3761c011733ad683 (diff) | |
mb/google/brya/var/redrix: Correct SSD power sequence
The current power sequencing for the SSD does not work in a non-serial
enabled BIOS image. It appears that the FSP scans the PCIe RPs before
the SSD has time to prepare itself for PCIe, so the FSP disables the RP
and so depthcharge cannot find a boot disk.
Changing the power sequence timing to enable power in bootblock and
deassert reset in ramstage follows the SSD's power sequence and
allows it to be discovered by the FSP so the RP does not get disabled.
BUG=b:199714453
TEST=build, boot into SSD, and run reboot stress test.
Change-Id: I5e7943a6cc88bc02bcbd97a1086b2d8044d7b1c3
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/redrix/gpio.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c index 7f284b051b..5e13576fc5 100644 --- a/src/mainboard/google/brya/variants/redrix/gpio.c +++ b/src/mainboard/google/brya/variants/redrix/gpio.c @@ -90,6 +90,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ @@ -102,8 +104,14 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* + * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and + * then deassert PERST# in ramstage + */ /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) |