diff options
| author | Tyler Wang <tyler.wang@quanta.corp-partner.google.com> | 2022-10-18 16:51:27 +0800 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2022-11-10 07:30:50 +0000 |
| commit | f346a17ce3f3a876e1ac2479b637aa99aa73824c (patch) | |
| tree | 237608cbfabd28fa27578fcfc44b0321af6ae34a /src/mainboard/google/brya/variants | |
| parent | 970e33a16811d61162b94b3e7b292d51791ee1f2 (diff) | |
mb/google/nissa/var/craask: Modify DPTF related settings
Request by thermal team, make below changes:
1) tdp_pl2_override: 12 --> 25
2) pl1.min_power: 3000 --> 5500
3) pl1.time_window_max: 32 * MSECS_PER_SEC --> 28 * MSECS_PER_SEC
4) pl2.min_power: 12000 --> 25000
5) pl2.max_power: 12000 --> 25000
6) pl2.time_window_min: 28 * MSECS_PER_SEC --> 1
7) pl2.time_window_max: 32 * MSECS_PER_SEC --> 1
BUG=b:239495499
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I88c8c4e6798ec5bc2930dd713e8c8b2c543cfaf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68523
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/overridetree.cb | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index fa79d8b569..57f4306e2e 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -112,13 +112,13 @@ chip soc/intel/alderlake register "power_limits_config[ADL_N_041_6W_CORE]" = "{ .tdp_pl1_override = 6, - .tdp_pl2_override = 12, + .tdp_pl2_override = 25, .tdp_pl4 = 78, }" register "power_limits_config[ADL_N_021_6W_CORE]" = "{ .tdp_pl1_override = 6, - .tdp_pl2_override = 12, + .tdp_pl2_override = 25, .tdp_pl4 = 78, }" @@ -149,17 +149,17 @@ chip soc/intel/alderlake register "controls.power_limits" = "{ .pl1 = { - .min_power = 3000, + .min_power = 5500, .max_power = 6000, .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, .granularity = 200 }, .pl2 = { - .min_power = 12000, - .max_power = 12000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, + .min_power = 25000, + .max_power = 25000, + .time_window_min = 1, + .time_window_max = 1, .granularity = 1000 } }" |