diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-16 14:34:31 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-24 21:28:57 +0000 |
| commit | ec11a6e5b1aac447321ee7eee23d90a93e0497df (patch) | |
| tree | 69b206b47776b1149458224e98fed31f30c33b71 /src/mainboard/google/brya/variants | |
| parent | 932783daf83e67f8838c20c5f5275782c9c28169 (diff) | |
mb/google/brya/var/agah: Reenable ASPM L1 substates
Now that the GPU CLKREQ# signal is working correctly, ASPM L1 substates
can be enabled and appear functional.
BUG=b:240390998
TEST=lspci reports them as functional, MODS does not hang
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8297f6bbf7f5a1f7d4ac519bc5b7b3112a74a9a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66811
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/overridetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index 91ee79d5c9..f8b1cc6934 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -81,7 +81,6 @@ chip soc/intel/alderlake .clk_req = 0, .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .pcie_rp_aspm = ASPM_L0S, }" device pci 00.0 alias dgpu on end end |