diff options
| author | Scott Chao <scott_chao@wistron.corp-partner.google.com> | 2021-12-21 14:18:31 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-21 16:29:13 +0000 |
| commit | e24b006ee4b45fc22c0eeae618f2d32102e36148 (patch) | |
| tree | 25eac3a0a0b1a020118de84be296532abbef3fe0 /src/mainboard/google/brya/variants | |
| parent | 25387927c052aadd07746723e6cff10ab2b40d29 (diff) | |
mb/google/brya/var/gimble{4es}: Decrease touchscreen T3 timing to 200ms
We set T3 as 300ms to meet Elan's spec, but the resume/suspend times
are greater than 500ms, which is the spec for Chromebooks.
The actual kernel timing has been measured, and given the ACPI delay
after deasserting reset in addition to the delay until the kernel
driver accesses the device, delaying only 200ms in the ACPI method is
also sufficient to meet the 300ms requirement.
BUG=b:210772498
BRANCH=none
TEST=build and test touchscreen function on DUT.
TEST=suspend, wake DUT and check touchscreen function.
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I4bb4eda09686cb59b6e19c741aa2b78d84332d2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/gimble/overridetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/gimble4es/overridetree.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 401909b43f..23071fe97a 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -198,7 +198,7 @@ chip soc/intel/alderlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "300" + register "generic.reset_delay_ms" = "200" register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb index 0b29e4d02d..0dd8c75934 100644 --- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb @@ -161,7 +161,7 @@ chip soc/intel/alderlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "300" + register "generic.reset_delay_ms" = "200" register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" |