diff options
| author | Shon Wang <shon.wang@quanta.corp-partner.google.com> | 2022-02-15 09:52:40 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-18 14:57:27 +0000 |
| commit | d91a6842bfb718779125920318a7b632d58506b0 (patch) | |
| tree | 4bfd200bc1dbcf03cd6ed7d7e7251a596e1a4700 /src/mainboard/google/brya/variants | |
| parent | d1275fb886d10c1bc007e1999a4f2204588a3a7a (diff) | |
mb/google/brya/var/vell: Correct MIPI camera info
The CIO2 port was incorrectly set to 2, while the correct port is 1
BUG=b:210801553
TEST=Build and boot on vell, camera works correctly now
Change-Id: I53d8448ed0e12777456af9b0bc65a04595b47e37
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61946
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/overridetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 15ba44ee87..9250dc65ca 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -136,7 +136,7 @@ chip soc/intel/alderlake register "cio2_num_ports" = "1" register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" - register "cio2_prt[0]" = "2" + register "cio2_prt[0]" = "1" device generic 0 on end end end |