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authorWeimin Wu <wuweimin@huaqin.corp-partner.google.com>2024-02-20 10:03:00 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-02-21 13:47:47 +0000
commitc6df1ac62c4cfd3284e4a454ffa53989c8f7ff6e (patch)
tree516912aed2981d32c1887935c17f956026058f29 /src/mainboard/google/brya/variants
parent3f06e6c74089a1dffcf9340890c7b5bb10ea2119 (diff)
mb/google/nissa/var/anraggar: Change tdp_pl1_override from 6 W to 15 W
Set tdp_pl1_override to 15 for performance required by the thermal team. Fix policies.critical index from 2 to 0. BUG=b:313833488 TEST=emerge-nissa coreboot Change-Id: I5341bd3d4842f9298a2f5d9e589918bb1b06ba69 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants')
-rw-r--r--src/mainboard/google/brya/variants/anraggar/overridetree.cb11
1 files changed, 9 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index 0fd63a72a3..77ae2b6782 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -134,6 +134,13 @@ chip soc/intel/alderlake
},
}"
+ # Power limit config
+ register "power_limits_config[ADL_N_041_6W_CORE]" = "{
+ .tdp_pl1_override = 15,
+ .tdp_pl2_override = 25,
+ .tdp_pl4 = 78,
+ }"
+
device domain 0 on
device ref dtt on
chip drivers/intel/dptf
@@ -155,8 +162,8 @@ chip soc/intel/alderlake
## Critical Policy
register "policies.critical" = "{
- [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
- [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN),
+ [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
+ [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN),
}"
register "controls.power_limits" = "{