diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2021-06-09 14:03:08 +0530 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-28 04:33:04 +0000 |
| commit | 9e23d017f555bad681c70f634bffd27c7ceccc2b (patch) | |
| tree | 2859a2e12c367714da4b966e436985a3972db05d /src/mainboard/google/brya/variants | |
| parent | b34950e68ab14a8b049f12b6934cc71e977729a8 (diff) | |
mb/google/brya: Update mainboard properties for BB retimer upgrade
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.
Reference CB:54292
BUG=b:186521258
TEST=Updated BB retimer FW from 3.4 to 3.5 without any device
connected.
Change-Id: I24a02fd446cb66bda9e66e59802b4deea6894273
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/brya0/overridetree.cb | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 81a4c34a59..3ba0abe9bb 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -134,6 +134,22 @@ chip soc/intel/alderlake device ref pcie_rp6 on probe DB_LTE LTE_PCIE end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp" = "{ + [0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4), + .group = ACPI_PLD_GROUP(1, 1),}}" + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp" = "{ + [0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4), + .group = ACPI_PLD_GROUP(3, 1)}}" + device generic 0 on end + end + end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" |