diff options
| author | Raihow Shi <raihow_shi@wistron.corp-partner.google.com> | 2022-06-27 13:20:47 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-05 13:06:45 +0000 |
| commit | 772ca3cc005125a2cbe0731493929041e61c20cb (patch) | |
| tree | 59318cc0c96e60ec9b58202134aa369cf7d5e9e7 /src/mainboard/google/brya/variants | |
| parent | fa7970aa81543cab7b508954a93a99e9bb6b6493 (diff) | |
mb/google/brask/variants/moli: set tcc_offset to 0℃
Set tcc_offset value to 0 in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.
BUG=b:236294162
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I8d4c631e07873923226683c8aa0cf36cb872e2d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/moli/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index ccfb478f01..6aa1ddc02f 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -27,6 +27,7 @@ chip soc/intel/alderlake register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # Enable USB2 Port4 register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port9 register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3 + register "tcc_offset" = "0" # TCC of 100C device domain 0 on device ref tcss_dma0 on chip drivers/intel/usb4/retimer |