diff options
| author | Wisley Chen <wisley.chen@quanta.corp-partner.google.com> | 2021-09-16 18:26:48 +0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-20 12:08:24 +0000 |
| commit | 58d2943c3a5a76d3435f0973a5d278aed19f2ada (patch) | |
| tree | 5171ef254471c4347853e8307a5caf9258c95f78 /src/mainboard/google/brya/variants | |
| parent | ea03d0047bbde9b2b4d3278470df6a8060640f4f (diff) | |
mb/google/brya/var/redrix: Update thermal table.
Update thermal setting from thermal team.
BUG=b:200134784
TEST=build and verified by thermal team.
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: If74c3bc19cf4abd64d646b842cbb6a61b910e933
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/redrix/overridetree.cb | 53 |
1 files changed, 10 insertions, 43 deletions
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index ea922e0b2a..b87e4c4082 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -84,42 +84,25 @@ chip soc/intel/alderlake register "options.tsr[0].desc" = ""DRAM"" register "options.tsr[1].desc" = ""Charger"" # TODO: below values are initial reference values only - ## Active Policy - register "policies.active" = "{ - [0] = { - .target = DPTF_CPU, - .thresholds = { - TEMP_PCT(85, 90), - TEMP_PCT(80, 80), - TEMP_PCT(75, 70), - } - } - }" ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), - }" - ## Critical Policy - register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [0] = DPTF_PASSIVE(CPU, CPU, 55, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 45, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 51, 5000), }" register "controls.power_limits" = "{ .pl1 = { - .min_power = 3000, + .min_power = 13000, .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, + .time_window_min = 42 * MSECS_PER_SEC, + .time_window_max = 42 * MSECS_PER_SEC, .granularity = 200, }, .pl2 = { - .min_power = 55000, - .max_power = 55000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, + .min_power = 35000, + .max_power = 35000, + .time_window_min = 42 * MSECS_PER_SEC, + .time_window_max = 42 * MSECS_PER_SEC, .granularity = 1000, } }" @@ -130,22 +113,6 @@ chip soc/intel/alderlake [2] = { 16, 1000 }, [3] = { 8, 500 } }" - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf" = "{ - [0] = { 90, 6700, 220, 2200, }, - [1] = { 80, 5800, 180, 1800, }, - [2] = { 70, 5000, 145, 1450, }, - [3] = { 60, 4900, 115, 1150, }, - [4] = { 50, 3838, 90, 900, }, - [5] = { 40, 2904, 55, 550, }, - [6] = { 30, 2337, 30, 300, }, - [7] = { 20, 1608, 15, 150, }, - [8] = { 10, 800, 10, 100, }, - [9] = { 0, 0, 0, 50, } - }" - ## Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" device generic 0 on end end end |