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authorSeunghwan Kim <sh_.kim@samsung.corp-partner.google.com>2024-04-01 14:44:48 +0900
committerSubrata Banik <subratabanik@google.com>2024-04-04 06:13:14 +0000
commit5462e8e943fde0c8d934a618eb2423f6bb6b6e84 (patch)
treed01c67b912efc4c183fdbd6850d823ce6ac7401d /src/mainboard/google/brya/variants
parent86b145ad3efed59e9b5ad4070caf2771d3af1d68 (diff)
mb/google/brya/var/xol: Reduce power limits according to battery status
When battery level is below critical level or battery is not present, cpus need to run with a power optimized configuration to avoid platform instabilities such as system power down. This will check the current battery status and configure cpu power limits using current PD power value. BUG=b:328729536 BRANCH=brya TEST=built and verified MSR PL2/PL4 values. Intel doc #614179 introduces how to check current PL values. [Original MSR PL1/PL2/PL4 register values for xol] cd /sys/class/powercap/intel-rapl/intel-rapl\:0/ grep . *power_limit* constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W) constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W) constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W) [When connected 60W adapter without battery] Before: constraint_0_power_limit_uw:15000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:114000000 After: constraint_0_power_limit_uw:15000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:60000000 [When connected 45W adapter without battery] Before: constraint_0_power_limit_uw:15000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:114000000 After: constraint_0_power_limit_uw:15000000 constraint_1_power_limit_uw:45000000 constraint_2_power_limit_uw:45000000 Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81614 Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants')
-rw-r--r--src/mainboard/google/brya/variants/xol/Makefile.mk1
-rw-r--r--src/mainboard/google/brya/variants/xol/ramstage.c58
2 files changed, 59 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/xol/Makefile.mk b/src/mainboard/google/brya/variants/xol/Makefile.mk
index 641e814351..c346b0abc9 100644
--- a/src/mainboard/google/brya/variants/xol/Makefile.mk
+++ b/src/mainboard/google/brya/variants/xol/Makefile.mk
@@ -3,3 +3,4 @@
bootblock-y += gpio.c
romstage-y += memory.c
ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/xol/ramstage.c b/src/mainboard/google/brya/variants/xol/ramstage.c
new file mode 100644
index 0000000000..135ac6043b
--- /dev/null
+++ b/src/mainboard/google/brya/variants/xol/ramstage.c
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/power_limit.h>
+
+#define DEFAULT_NO_BATTERY_POWER_LIMIT_WATTS 30
+
+static bool get_pd_power_watts(u32 *watts)
+{
+ int rv;
+ enum usb_chg_type type = USB_CHG_TYPE_UNKNOWN;
+ u16 volts_mv, current_ma;
+
+ rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
+ if (rv == 0 && type == USB_CHG_TYPE_PD) {
+ /* Detected USB-PD. Base on max value of adapter */
+ *watts = ((u32)current_ma * volts_mv) / 1000000;
+ return true;
+ }
+
+ printk(BIOS_WARNING, "Cannot get PD power info. rv = %d, usb_chg_type: %d\n", rv, type);
+ return false;
+}
+
+void variant_devtree_update(void)
+{
+ struct soc_power_limits_config *soc_config;
+ u32 watts;
+
+ soc_config = variant_get_soc_power_limit_config();
+ if (soc_config == NULL)
+ return;
+
+ /*
+ * If battery is not present or battery level is at or below critical threshold
+ * to boot a platform with the power efficient configuration, limit PL2 and PL4
+ * settings.
+ */
+ if (!google_chromeec_is_battery_present_and_above_critical_threshold()) {
+ /* Use fixed value when we cannot get the current PD power */
+ if (!get_pd_power_watts(&watts))
+ watts = DEFAULT_NO_BATTERY_POWER_LIMIT_WATTS;
+
+ printk(BIOS_INFO, "override PL2 and PL4 settings to %d watts\n", watts);
+
+ if (soc_config->tdp_pl2_override > watts)
+ soc_config->tdp_pl2_override = watts;
+
+ if (soc_config->tdp_pl4 > watts)
+ soc_config->tdp_pl4 = watts;
+ }
+}