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authorRaihow Shi <raihow_shi@wistron.corp-partner.google.com>2022-08-10 21:20:21 +0800
committerMartin L Roth <gaumless@gmail.com>2022-08-13 16:41:13 +0000
commit41714ed5413313723dc7876bc0f27c09dc38dc6b (patch)
tree7c5becfda3696c1a34095f96e1c59ffc8f73af91 /src/mainboard/google/brya/variants
parentd9142921429ec34dd64de9372242bfdd301969c8 (diff)
mb/google/brask/variants/moli: modify psys_pl2 for 15W and 28W SOC
Moli has 90W adapter for 15W SOC and 135W adapter for 28W SOC, so modify the Psys_PL2 for both 15W and 28W SOC. -set 90W Psys_PL2 for 15W SOC -set 135W Psys_PL2 for 28W SOC BUG=b:242119726 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: If8f9006d797d74f6d5d802d445edc425a4700420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants')
-rw-r--r--src/mainboard/google/brya/variants/moli/ramstage.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/variants/moli/ramstage.c b/src/mainboard/google/brya/variants/moli/ramstage.c
index b9d6f8f74c..77bf3aea7a 100644
--- a/src/mainboard/google/brya/variants/moli/ramstage.c
+++ b/src/mainboard/google/brya/variants/moli/ramstage.c
@@ -20,10 +20,10 @@ const struct cpu_power_limits limits[] = {
const struct system_power_limits sys_limits[] = {
/* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
- { PCI_DID_INTEL_ADL_P_ID_10, 15, 135 },
- { PCI_DID_INTEL_ADL_P_ID_7, 15, 135 },
- { PCI_DID_INTEL_ADL_P_ID_6, 15, 135 },
- { PCI_DID_INTEL_ADL_P_ID_5, 28, 230 },
+ { PCI_DID_INTEL_ADL_P_ID_10, 15, 90 },
+ { PCI_DID_INTEL_ADL_P_ID_7, 15, 90 },
+ { PCI_DID_INTEL_ADL_P_ID_6, 15, 90 },
+ { PCI_DID_INTEL_ADL_P_ID_5, 28, 135 },
};
const struct psys_config psys_config = {