diff options
| author | Simon Yang <simon1.yang@intel.com> | 2023-11-22 09:27:38 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-01-17 09:44:29 +0000 |
| commit | 01bad20fab0ac62c13ff331013e4751051ec0cfe (patch) | |
| tree | 00b67ee9f7fdd270d274736f303f5ac55c68f570 /src/mainboard/google/brya/variants | |
| parent | d1a940c7534d14e62d6647e27b255544b60939ca (diff) | |
mb/google/nissa/var/gothrax: Tune eMMC DLL values
Gothrax cannot boot into OS with a kernel loading failure.
Update eMMC DLL values to improve initialization reliability
How to get these values:
- Sending different speed TX/RX command/data signal to eMMC and check
the response is successful or not.
- Collecting above results from each eMMC model that project used.
- Analysing logs to provide a fine tuned DLL values.
BUG=b:310701323
TEST=Cold reboot stress test over 2500 cycles
Change-Id: Ie36cc9948e3d5dee46385e584baad141a249be79
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/gothrax/overridetree.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/gothrax/overridetree.cb b/src/mainboard/google/brya/variants/gothrax/overridetree.cb index bb333aaebe..b36ff07453 100644 --- a/src/mainboard/google/brya/variants/gothrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/gothrax/overridetree.cb @@ -55,7 +55,7 @@ chip soc/intel/alderlake # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1D1B" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-42.3.12. @@ -66,13 +66,13 @@ chip soc/intel/alderlake # 11: Reserved # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004c" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10005" # EMMC Rx Strobe Delay # Refer to EDS-Vol2-42.3.11. # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC. # Bit 2 - C1 has a redriver which does SBU muxing. |