diff options
| author | Kangheui Won <khwon@chromium.org> | 2022-05-27 15:45:03 +1000 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-05-31 13:42:20 +0000 |
| commit | c8c648f111b51b7360e24308caad7bfa19cc8589 (patch) | |
| tree | 158cabd8e688d09098730c42916d4fadca75938e /src/mainboard/google/brya/chromeos-nissa-32MiB.fmd | |
| parent | b3f91b79414c8ad49db80ca6b1c7036a951edfbb (diff) | |
mb/google/nissa: Add and default to 16 MB layout
Future nissa devices will mostly use 16MB SPI flash. Add 16MB layout and
make it default for nissa.
BUG=b:202783191
TEST=build nissa and brya firmware, check they're still 32MB
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I04ae46d62d3e018610ca2533c186dda980bd67bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/chromeos-nissa-32MiB.fmd')
| -rw-r--r-- | src/mainboard/google/brya/chromeos-nissa-32MiB.fmd | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd b/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd new file mode 100644 index 0000000000..5d386f916b --- /dev/null +++ b/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd @@ -0,0 +1,59 @@ +FLASH 32M { + SI_ALL 3776K { + SI_DESC 4K + SI_ME { + CSE_LAYOUT 8K + CSE_RO 1360K + CSE_DATA 420K + # 64-KiB aligned to optimize RW erases during CSE update. + CSE_RW 1984K + } + } + SI_BIOS 28992K { + RW_SECTION_A 4344K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 1434K + } + RW_LEGACY(CBFS) 1M + RW_MISC 152K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 8K + } + # RW UNUSED Region 1. + RW_UNUSED_1 7088K + # This section starts at the 16M boundary in SPI flash. + # ADL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 4344K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 1434K + } + # RW UNUSED Region 2. + RW_UNUSED_2 7944K + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} |