diff options
| author | Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> | 2022-11-16 12:46:06 +0530 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2022-11-18 03:39:35 +0000 |
| commit | 1c6b02a8b60470a94301e3034707af88b9980c96 (patch) | |
| tree | 4f5688dc1c08bbfa3e081dab154841992e415da3 /src/mainboard/google/brya/chromeos-nissa-32MiB.fmd | |
| parent | d7328abc9589008bb0258ed214b9d97bda42ad79 (diff) | |
mb/google/nissa: Modify FMD to redistribute buffer
Modify the chromeos FMD file for nissa variants to redistribute the
buffer in SI_ME region obtained due to CSE size optimizations to SI_BIOS
region.
1. Modify SI_ALL region size to 3712K. SI_DESC remains at 4K and SI_ME
is 3708K.
2. Modify SI_BIOS region to 12672K. This results in an addition of 32K
buffer each to FW_MAIN_A/B regions.
BUG=b:228936671
BRANCH=firmware-nissa-15217.B
TEST=Verify CSE FW update with new FMD and ME RW blobs on craask.
Cq-Depend: chrome-internal:5094491
Change-Id: I5ead2f81850a2aa79e677c7f271db672e235750a
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/chromeos-nissa-32MiB.fmd')
| -rw-r--r-- | src/mainboard/google/brya/chromeos-nissa-32MiB.fmd | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd b/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd index 48406b9f21..1662600e70 100644 --- a/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd +++ b/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd @@ -1,10 +1,10 @@ FLASH 32M { - SI_ALL 3776K { + SI_ALL 3712K { SI_DESC 4K SI_ME } - SI_BIOS 28992K { - RW_SECTION_A 4344K { + SI_BIOS 29056K { + RW_SECTION_A 4376K { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 @@ -24,19 +24,19 @@ FLASH 32M { RW_NVRAM(PRESERVE) 8K } # RW UNUSED Region 1. - RW_UNUSED_1 7088K + RW_UNUSED_1 7120K # This section starts at the 16M boundary in SPI flash. # ADL does not support a region crossing this boundary, # because the SPI flash is memory-mapped into two non- # contiguous windows. - RW_SECTION_B 4344K { + RW_SECTION_B 4376K { VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 ME_RW_B(CBFS) 1434K } # RW UNUSED Region 2. - RW_UNUSED_2 7944K + RW_UNUSED_2 7912K # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 4M { |