diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-16 14:18:35 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-18 18:28:04 +0000 |
| commit | bcc3059d83b7503a3247690a895a05127102d414 (patch) | |
| tree | e4bc9164ab74f4946444d3d1966803fc726689ad /src/mainboard/google/brya/acpi | |
| parent | c1de4b456b9fe9a4b79112e103ce5ee41ba837f7 (diff) | |
mb/google/brya/var/agah: Update NVVDD VR PGOOD GPIO
For board revs 3 and later, the PG pin for the NVVDD VR moved from
GPP_E16 to GPP_E3. To accommodate this, the DSDT contains a Name that
this code will write the correct GPIO # to depending on the board rev,
and we'll use that instead.
BUG=b:239721380
TEST=still works on board rev 2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I11aec6069da8e086789419303871c6d0f5fb29af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/acpi')
| -rw-r--r-- | src/mainboard/google/brya/acpi/power.asl | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl index 618030b4fd..8a4dd742b0 100644 --- a/src/mainboard/google/brya/acpi/power.asl +++ b/src/mainboard/google/brya/acpi/power.asl @@ -7,7 +7,6 @@ #define GPIO_NV33_PWR_EN GPP_A21 #define GPIO_NV33_PG GPP_A22 #define GPIO_NVVDD_PWR_EN GPP_E0 -#define GPIO_NVVDD_PG GPP_E16 #define GPIO_PEXVDD_PWR_EN GPP_E10 #define GPIO_PEXVDD_PG GPP_E17 #define GPIO_FBVDD_PWR_EN GPP_A19 @@ -22,6 +21,15 @@ /* 250ms in "Timer" units (i.e. 100ns increments) */ #define MIN_OFF_TIME_TIMERS 2500000 +/* + * For board revs 3 and later, the PG pin for the NVVDD VR moved from + * GPP_E16 to GPP_E3. To accommodate this, this DSDT contains a Name + * that the `variant.c` code will write the correct GPIO # to depending + * on the board rev, and we'll use that instead. + */ +/* Dynamically-assigned NVVDD PG GPIO, set in _INI in SSDT */ +Name (NVPG, 0) + /* Optimus Power Control State */ Name (OPCS, OPTIMUS_POWER_CONTROL_DISABLE) @@ -72,7 +80,7 @@ Method (GC6I, 0, Serialized) /* Deassert EN_PPVAR_GPU_NVVDD */ \_SB.PCI0.CTXS (GPIO_NVVDD_PWR_EN) - GPPL (GPIO_NVVDD_PG, 0, 20) + GPPL (NVPG, 0, 20) Sleep (2) /* Assert GPU_PERST_L */ @@ -95,7 +103,7 @@ Method (GC6O, 0, Serialized) /* Ramp up NVVDD */ \_SB.PCI0.STXS (GPIO_NVVDD_PWR_EN) - GPPL (GPIO_NVVDD_PG, 1, 4) + GPPL (NVPG, 1, 4) /* Ramp up PEXVDD */ \_SB.PCI0.STXS (GPIO_PEXVDD_PWR_EN) @@ -141,7 +149,7 @@ Method (PGON, 0, Serialized) /* Ramp up NVVDD rail */ \_SB.PCI0.STXS (GPIO_NVVDD_PWR_EN) - GPPL (GPIO_NVVDD_PG, 1, 5) + GPPL (NVPG, 1, 5) /* Ramp up PEXVDD rail */ \_SB.PCI0.STXS (GPIO_PEXVDD_PWR_EN) @@ -190,7 +198,7 @@ Method (PGOF, 0, Serialized) /* Ramp down NVVDD and let rail discharge to <10% */ \_SB.PCI0.CTXS (GPIO_NVVDD_PWR_EN) - GPPL (GPIO_NVVDD_PG, 0, 20) + GPPL (NVPG, 0, 20) Sleep (2) /* Ramp down NV33 and let rail discharge to <10% */ |