diff options
| author | Tarun Tuli <taruntuli@google.com> | 2023-03-29 13:36:26 +0000 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-04-11 14:34:41 +0000 |
| commit | 166387f7903299287cea9537a3758ab66b56f42e (patch) | |
| tree | e6091f7644a23e9d8ce7199d7a1edc15c9017609 /src/mainboard/google/brya/acpi | |
| parent | fa38535a20bdfcf0a27862fc13d2e02a09da8ef8 (diff) | |
mb/google/brya/variants/hades: Update GPU power sequencing to add Hades support
Add GPU power sequencing changes for the Hades baseboard and variant.
Some signals were added, moved or inverted.
Based on implementation from Agah.
Moved signals:
GPIO_1V8_PWR_EN GPP_E11
GPIO_NV33_PWR_EN GPP_E2
GPIO_NV33_PG GPP_E1
New signals:
GPIO_NV12_PWR_EN GPP_D0
GPIO_NV12_PG GPP_D1
Inverted signals:
GPIO_FBVDD_PWR_EN GPP_A19
ifdef's will be dropped once the Agah variant is retired.
BUG=b:269371363
TEST=builds and verified on Agah that DGPU is still detectable (lspci)
Change-Id: I0b8efe7a34102cf61d4f784103c4a4f9337213f7
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/acpi')
| -rw-r--r-- | src/mainboard/google/brya/acpi/power.asl | 36 |
1 files changed, 33 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl index bd000fbb5b..23759f6b36 100644 --- a/src/mainboard/google/brya/acpi/power.asl +++ b/src/mainboard/google/brya/acpi/power.asl @@ -5,10 +5,23 @@ External (\_SB.PCI0.PMC.IPCS, MethodObj) /* Voltage rail control signals */ + +#if CONFIG(BOARD_GOOGLE_AGAH) #define GPIO_1V8_PWR_EN GPP_F12 -#define GPIO_1V8_PG GPP_E20 + #define GPIO_NV33_PWR_EN GPP_A21 #define GPIO_NV33_PG GPP_A22 +#else +#define GPIO_1V8_PWR_EN GPP_E11 + +#define GPIO_NV33_PWR_EN GPP_E2 +#define GPIO_NV33_PG GPP_E1 +#endif + +#define GPIO_1V8_PG GPP_E20 +#define GPIO_NV12_PWR_EN GPP_D0 +#define GPIO_NV12_PG GPP_D1 + #define GPIO_NVVDD_PWR_EN GPP_E0 #define GPIO_PEXVDD_PWR_EN GPP_E10 #define GPIO_PEXVDD_PG GPP_E17 @@ -197,6 +210,10 @@ Method (PGON, 0, Serialized) /* Assert PERST# */ CTXS (GPIO_GPU_PERST_L) + /* Ramp up 1.2V rail on boards with support */ + STXS (GPIO_NV12_PWR_EN) + GPPL (GPIO_NV12_PG, 1, 5) + /* Ramp up 1.8V rail */ STXS (GPEN) GPPL (GPIO_1V8_PG, 1, 20) @@ -213,8 +230,13 @@ Method (PGON, 0, Serialized) STXS (GPIO_PEXVDD_PWR_EN) GPPL (GPIO_PEXVDD_PG, 1, 5) - /* Ramp up FBVDD rail (active low) */ + /* Ramp up FBVDD rail */ +#if CONFIG(BOARD_GOOGLE_AGAH) CTXS (GPIO_FBVDD_PWR_EN) +#else + STXS (GPIO_FBVDD_PWR_EN) +#endif + GPPL (GPIO_FBVDD_PG, 1, 5) /* All rails are good */ @@ -239,8 +261,12 @@ Method (PGOF, 0, Serialized) CTXS (GPIO_GPU_ALLRAILS_PG) Sleep (1) - /* Ramp down FBVDD (active-low) and let rail discharge to <10% */ + /* Ramp down FBVDD and let rail discharge to <10% */ +#if CONFIG(BOARD_GOOGLE_AGAH) STXS (GPIO_FBVDD_PWR_EN) +#else + CTXS (GPIO_FBVDD_PWR_EN) +#endif GPPL (GPIO_FBVDD_PG, 0, 20) /* Ramp down PEXVDD and let rail discharge to <10% */ @@ -262,6 +288,10 @@ Method (PGOF, 0, Serialized) CTXS (GPEN) GPPL (GPIO_1V8_PG, 0, 20) + /* Ramp down 1.2V rail on boards with support */ + STXS (GPIO_NV12_PWR_EN) + GPPL (GPIO_NV12_PG, 0, 5) + GCOT = Timer GPPS = GPU_POWER_STATE_OFF |