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authorSubrata Banik <subratabanik@google.com>2024-08-29 13:49:03 +0530
committerSubrata Banik <subratabanik@google.com>2024-09-02 03:51:11 +0000
commitf51885d370f4af0a03cec4e6ea85d99d81575fc4 (patch)
tree5140d696cf78dffeac7d2202acd3268345d03904 /src/mainboard/google/brya/Kconfig
parent09ea33cdd81aece1069b12a557d45da2320b3ed4 (diff)
mb/google/brya: Add romstage early graphics for trulo baseboard
1) Add all required changes for eSOL support. 2) Select MAINBOARD_USE_EARLY_LIBGFXINIT for Trulo. The CSOT (MNC207QS1-1) panel is used for the devicetree. BUG=b:362895813 TEST=On-screen text message seen during MRC training on Trulo SKU1. MRC: no data in 'RW_MRC_CACHE' bootmode is set to: 0 DP PHY mode status not complete DP PHY mode status not complete DP PHY mode status not complete ... Informing user on-display of memory training Change-Id: Ic34a8601b3084aa5f780d358fb0b15b7e820d375 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84128 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/Kconfig')
-rw-r--r--src/mainboard/google/brya/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index f4c6f7cece..b54b0dba42 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -113,6 +113,7 @@ config BOARD_GOOGLE_BASEBOARD_TRULO
select DRIVERS_AUDIO_SOF
select DRIVERS_INTEL_ISH
select MAINBOARD_DISABLE_STAGE_CACHE
+ select MAINBOARD_HAS_EARLY_LIBGFXINIT
select MEMORY_SOLDERDOWN
select SOC_INTEL_COMMON_MMC_OVERRIDE
select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW