diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2023-03-12 12:24:58 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-04-04 08:07:56 +0000 |
| commit | 94050499ca9fa1b1ebb7a867eea3f722a4ca85c9 (patch) | |
| tree | d90306b162dcf5e1cd50203fd139643190529b6e /src/mainboard/google/brya/Kconfig | |
| parent | fb1b192cf1c101dad40991081e406dddf52bd7fd (diff) | |
soc/intel/alderlake: Add support for CSE timestamp data versions
CSE performance data timestamps are different for version 1
Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch
moves the current ADL/RPL timestamp definitions to a separate
header file. It marks current structure as version 1.
BUG=b:259366109
TEST=Boot to OS, check ADL/RPL pre-cpu timestamps.
Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Diffstat (limited to 'src/mainboard/google/brya/Kconfig')
| -rw-r--r-- | src/mainboard/google/brya/Kconfig | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1534a5456c..e588524e62 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -36,6 +36,7 @@ config BOARD_GOOGLE_BRYA_COMMON select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE select SOC_INTEL_CRASHLOG + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1 if SOC_INTEL_ALDERLAKE_PCH_P config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n @@ -44,7 +45,6 @@ config BOARD_GOOGLE_BASEBOARD_BRYA select HAVE_SLP_S0_GATE select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE select SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 @@ -59,7 +59,6 @@ config BOARD_GOOGLE_BASEBOARD_BRASK select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select TPM_GOOGLE_CR50 select CR50_RESET_CLEAR_EC_AP_IDLE_FLAG @@ -70,7 +69,6 @@ config BOARD_GOOGLE_BASEBOARD_HADES select HAVE_SLP_S0_GATE select MEMORY_SODIMM select SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select SOC_INTEL_RAPTORLAKE select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 |