diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2021-07-23 11:36:33 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-04 18:41:03 +0000 |
| commit | 126162c38f47cab8569cae70373d5b512e071c14 (patch) | |
| tree | 7cfa4ebcb040d250cfd3132d2ce1e3846204d867 /src/mainboard/google/brya/Kconfig | |
| parent | 4a48dbe60bb39b2114f1a4c9bfc02a8d1a8e258f (diff) | |
mb/google/brya: Enable DDR4 SODIMM for brask
Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in
brask device tree and add SPD addressese for the two DIMMs.
Separate the Kconfig items of brya and brask. Move
HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya
and add config SPD_CACHE_IN_FMAP to brask.
Add a new section RW_SPD_CACHE to fmd for caching SPD data.
The renamed romstage.c is used by both brya and brask and a new
function variant_get_spd_info is provided to support the different
SPD source types.
BUG=b:194055762
BRANCH=None
TEST=build pass
Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/Kconfig')
| -rw-r--r-- | src/mainboard/google/brya/Kconfig | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 5f53c692c9..e6e44e2f56 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,10 +1,12 @@ config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n - select ROMSTAGE_SPD_CBFS + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS + select HAVE_SPD_IN_CBFS select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_BASEBOARD_BRASK def_bool n + select SPD_CACHE_IN_FMAP if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK @@ -50,7 +52,6 @@ config BASEBOARD_DIR default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK config CHROMEOS - select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE select VBOOT_LID_SWITCH @@ -118,10 +119,6 @@ config UART_FOR_CONSOLE int default 0 -config ROMSTAGE_SPD_CBFS - def_bool n - select HAVE_SPD_IN_CBFS - config HAVE_WWAN_POWER_SEQUENCE def_bool n help |