diff options
| author | Wentao Qin <qinwentao@huaqin.corp-partner.google.com> | 2024-09-07 15:09:23 +0800 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2024-09-10 15:08:48 +0000 |
| commit | e67aaf2da62db488f6e8dbe046bc844c458b18c0 (patch) | |
| tree | a5c92880e557739c4eff6385ba1751c644371dd5 /src/mainboard/google/brox | |
| parent | 45c1e249bf3beb84276f34e958db73380c32b0c8 (diff) | |
mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU
Check that lnkCap supports ASPM L1, so set it to ASPM_L1
to avoid excessive power consumption.
BUG=b:364484621, b:361828368
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
w/o this CL -
```
lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl"
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+
```
w/ this CL -
```
lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl"
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
```
Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84241
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brox')
| -rw-r--r-- | src/mainboard/google/brox/variants/lotso/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb index 85a35065f1..2970635b63 100644 --- a/src/mainboard/google/brox/variants/lotso/overridetree.cb +++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb @@ -326,6 +326,7 @@ chip soc/intel/alderlake .clk_req = 0, .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L1, }" probe STORAGE STORAGE_NVME probe unprovisioned |