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authorDuncan Laurie <dlaurie@chromium.org>2013-06-24 14:57:40 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-12-12 22:12:09 +0100
commit3ece50d9db35eecef557fc6ad8cc404224cfc9ac (patch)
tree704280460756465755f37a12830167e38865843d /src/mainboard/google/bolt/ec.c
parent0a7c49efa02b770f9f4f723633f82784be7ae6b8 (diff)
bolt: Initial mainboard commit
BUG=chrome-os-partner:20448 BRANCH=none TEST=emerge-bolt chromeos-coreboot-bolt Change-Id: I634a755ac7659e7a977b51bcc061f69eb8263810 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59843 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4330 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/google/bolt/ec.c')
-rw-r--r--src/mainboard/google/bolt/ec.c52
1 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/google/bolt/ec.c b/src/mainboard/google/bolt/ec.c
new file mode 100644
index 0000000000..0919f0feec
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+++ b/src/mainboard/google/bolt/ec.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/acpi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <types.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+void mainboard_ec_init(void)
+{
+ printk(BIOS_DEBUG, "mainboard_ec_init\n");
+ post_code(0xf0);
+
+ /* Restore SCI event mask on resume. */
+ if (acpi_slp_type == 3) {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S3_WAKE_EVENTS);
+
+ /* Disable SMI and wake events */
+ google_chromeec_set_smi_mask(0);
+
+ /* Clear pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ } else {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+ }
+
+ /* Clear wake events, these are enabled on entry to sleep */
+ google_chromeec_set_wake_mask(0);
+
+ post_code(0xf1);
+}