diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-11 13:59:12 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-02-12 19:48:34 +0000 |
| commit | a3c6ed0dffe144ca1803b43fe1e0e16a9136793e (patch) | |
| tree | a8a8bb08065dc46bc3621819cf14414db389e70b /src/mainboard/google/beltino | |
| parent | 33b59c9170a66a7f6d9c26ccf664714ea81d218d (diff) | |
haswell boards: Correct USB config indentation
Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50539
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/beltino')
| -rw-r--r-- | src/mainboard/google/beltino/romstage.c | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index f009f5abe1..dda2edc8d5 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -46,30 +46,30 @@ void mb_get_spd_map(uint8_t spd_map[4]) spd_map[2] = 0xa4; } - const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { - /* Length, Enable, OCn#, Location */ - { 0x0064, 1, 0, /* P0: VP8 */ - USB_PORT_MINI_PCIE }, - { 0x0040, 1, 0, /* P1: Port A, CN22 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, 1, /* P2: Port B, CN23 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */ - USB_PORT_INTERNAL }, - { 0x0040, 1, 2, /* P4: Port C, CN25 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, 2, /* P5: Port D, CN25 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */ - USB_PORT_INTERNAL }, - { 0x0000, 0, 0, /* P7: N/C */ - USB_PORT_SKIP }, - }; +const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0064, 1, 0, /* P0: VP8 */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 0, /* P1: Port A, CN22 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, 1, /* P2: Port B, CN23 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */ + USB_PORT_INTERNAL }, + { 0x0040, 1, 2, /* P4: Port C, CN25 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, 2, /* P5: Port D, CN25 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */ + USB_PORT_INTERNAL }, + { 0x0000, 0, 0, /* P7: N/C */ + USB_PORT_SKIP }, +}; - const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { - /* Enable, OCn# */ - { 1, 0 }, /* P1; CN22 */ - { 1, 1 }, /* P2; CN23 */ - { 1, 2 }, /* P3; CN25 */ - { 1, 2 }, /* P4; CN25 */ - }; +const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; CN22 */ + { 1, 1 }, /* P2; CN23 */ + { 1, 2 }, /* P3; CN25 */ + { 1, 2 }, /* P4; CN25 */ +}; |