diff options
| author | Kane Chen <kane.chen@intel.corp-partner.google.com> | 2023-10-05 14:03:53 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-09 13:42:01 +0000 |
| commit | 70b517ee5791fb4c5136231304f8cf1d734c66a9 (patch) | |
| tree | 02c1f8e6e6e9012942a7323d9f0fac41e0b6dc3b /src/mainboard/google/beltino/smihandler.c | |
| parent | 0177c95c16e5413f832200bfd4cf8a0e5adcfbe5 (diff) | |
soc/intel/meteorlake: Reserve IOE P2SB MMIO correctly
The original code only reserves IOM mmio, but there is other asl
code that requires to program ioe p2sb mmio such as IOE PCIE clk request
control. See \_SB.ECLK.CLKD in src/soc/intel/common/acpi/pcie_clk.asl
TEST=as before: suspend_stress_test 50 cycle pass, type-c display OK
on screebo
Change-Id: Ie55f7975277b390f776e44596c42e426ba9cd235
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78252
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard/google/beltino/smihandler.c')
0 files changed, 0 insertions, 0 deletions