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| author | Shuo Liu <shuo.liu@intel.com> | 2023-03-29 03:16:58 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-10-18 16:44:47 +0000 |
| commit | 1a82871cc0d2f1cca8dceb0bba13d036fedba802 (patch) | |
| tree | 17009d160f766fae181fde35c7e1118661e5d2ee /src/mainboard/google/beltino/smihandler.c | |
| parent | ae46d6ddaa0e3ffcfb14fe315c70c86d1591656b (diff) | |
soc/xeon_sp: Initially add N-1 IBL codes
N-1 IBL (Integrated Boot Logic) codes are initially forked from
EBG (Emmitsburg PCH) codes (src/soc/intel/xeon_sp/ebg). N-1 IBL
codes are a set of stub codes to fulfill build sanity check for GNR
SoC and CRB codes before the formal codes are published.
Change-Id: I6bd5a2ed973ff91750c5ed1f9a57d30e41d8b97e
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/mainboard/google/beltino/smihandler.c')
0 files changed, 0 insertions, 0 deletions