diff options
| author | Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> | 2024-09-01 12:49:33 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-09-04 04:38:43 +0000 |
| commit | 2e1b7d3a151f37f90ecfc22bbe0236e1a6c918bd (patch) | |
| tree | 6784887c2812311da9864ced558f996df3e9cdec /src/mainboard/google/beltino/chromeos.fmd | |
| parent | 500b335b10ba671558b9851087626abbbcf556b7 (diff) | |
include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro
Details:
- Add (TM1_TM2_EMTTM_ENABLE_BIT) - Offset 0x1a0 required bits
- Add (IA32_PACKAGE_THERM_INTERRUPT) – Offset 0x1b2 required bits
Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84174
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Diffstat (limited to 'src/mainboard/google/beltino/chromeos.fmd')
0 files changed, 0 insertions, 0 deletions