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author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2024-02-14 13:23:28 +0100 |
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committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-06-08 08:18:26 +0000 |
commit | ca5254acc0d55199254a270496c955249ad244d1 (patch) | |
tree | 342666bf51e850062f672a253dcb5a398e4d8979 /src/mainboard/google/beltino/Makefile.mk | |
parent | f0fb3af828b3b457c4487a174440e6f6b6d073ca (diff) |
soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree
The UsbTcPortEn UPD for FSP-S is being set in ramstage, however the
equivalent FSP-M UPD, the UsbTcPortEnPreMem, was not being set.
Following the Meteor Lake example, set the UsbTcPortEnPreMem UPD
as well for Alder Lake.
Setting this FSP-M UPD will cause FSP to properly program sideband
use BSSB_LSx pins for the enabled Type-C ports. Required for proper
DCI debug and TCSS initialization flow.
Change-Id: If3b79167ec1769ddfb7d28a6c78a3e80bd10afe7
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80500
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/mainboard/google/beltino/Makefile.mk')
0 files changed, 0 insertions, 0 deletions