diff options
| author | Hsuan-ting Chen <roccochen@google.com> | 2021-10-07 06:21:28 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-15 13:00:32 +0000 |
| commit | adb393bdd6cd6734fa2672bd174aca4588a68016 (patch) | |
| tree | 584f20ba1cadcb3b36c856d501d4a7b3d4eeb047 /src/mainboard/google/auron | |
| parent | 82130369a1c8b06b0aa5e804096d93b98ffce7cc (diff) | |
Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
This reverts commit 6260bf712a836762b18d80082505e981e040f4bc.
Reason for revert: This CL did not handle Intel GPIO correctly. We need
to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel
SoC.
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/auron')
| -rw-r--r-- | src/mainboard/google/auron/chromeos.c | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index f449c9cf7f..50eeddce0a 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -8,13 +8,6 @@ /* SPI Write protect is GPIO 16 */ #define CROS_WP_GPIO 58 -/* EC_IN_RW is GPIO 25 in samus and 14 otherwise */ -#if CONFIG(BOARD_GOOGLE_SAMUS) -#define EC_IN_RW_GPIO 25 -#else -#define EC_IN_RW_GPIO 14 -#endif - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -39,9 +32,3 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !get_gpio(EC_IN_RW_GPIO); -} |