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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-11-05 22:02:26 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-11-12 11:23:00 +0000
commit4bcc275d717c5c2ab926bc1ee2cb7122f58928e2 (patch)
tree72da4446470d3221ce728b6f4f8db48dbf2ed1b8 /src/mainboard/google/auron
parent4cdac3c7b3e03d85377f039cbd6cc677bf91acd9 (diff)
mb/google,intel: Add ChromeOS GPIOs to onboard.h
Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/auron')
-rw-r--r--src/mainboard/google/auron/chromeos.c3
-rw-r--r--src/mainboard/google/auron/onboard.h9
2 files changed, 10 insertions, 2 deletions
diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c
index 3132fd7da5..40f98f20eb 100644
--- a/src/mainboard/google/auron/chromeos.c
+++ b/src/mainboard/google/auron/chromeos.c
@@ -7,8 +7,7 @@
#include <soc/chromeos.h>
#include <southbridge/intel/lynxpoint/lp_gpio.h>
-/* SPI Write protect is GPIO 16 */
-#define CROS_WP_GPIO 58
+#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios)
{
diff --git a/src/mainboard/google/auron/onboard.h b/src/mainboard/google/auron/onboard.h
new file mode 100644
index 0000000000..6d4ff28dd8
--- /dev/null
+++ b/src/mainboard/google/auron/onboard.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AURON_ONBOARD_H
+#define AURON_ONBOARD_H
+
+/* SPI Write protect is GPIO 58 */
+#define CROS_WP_GPIO 58
+
+#endif