diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-12-02 15:30:10 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-08-16 17:55:02 +0000 |
| commit | 027f86e6af023b338a0f1d8a999a8f33eeacb010 (patch) | |
| tree | 691450089ec0116cba1ec04b1b73ca3dea39aaf5 /src/mainboard/google/auron | |
| parent | 4a9de553c5307595f396b47aaa108bf1dc34638d (diff) | |
ACPI: Add usb_charge_mode_from_gnvs()
Early Chromebook generations stored the information about
USB port power control for S3/S5 sleepstates in GNVS, although
the configuration is static.
Reduce code duplication and react to ACPI S4 as if it was ACPI
S5 request.
Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/google/auron')
| -rw-r--r-- | src/mainboard/google/auron/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/auron/acpi_tables.c | 4 | ||||
| -rw-r--r-- | src/mainboard/google/auron/smihandler.c | 18 |
3 files changed, 5 insertions, 18 deletions
diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index f503d465e8..e7ba578fec 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -1,5 +1,6 @@ config BOARD_GOOGLE_BASEBOARD_AURON def_bool n + select ACPI_GNVS_USB_CHARGECTL select BOARD_ROMSIZE_KB_8192 select BROADWELL_LPDDR3 if BOARD_GOOGLE_SAMUS select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index 501f54b4cf..048de76a20 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -10,9 +10,7 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; + gnvs->s3u1 = gnvs->s3u0; gnvs->tmps = CTL_TDP_SENSOR_ID; gnvs->tcrt = CRITICAL_TEMPERATURE; diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 237a2b3c31..0fc3588020 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -8,7 +8,6 @@ #include <ec/google/chromeec/smm.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <soc/iomap.h> -#include <soc/nvs.h> #include "ec.h" #include <variant/onboard.h> @@ -36,28 +35,17 @@ static void mainboard_disable_gpios(void) void mainboard_smi_sleep(u8 slp_typ) { /* Disable USB charging if required */ + /* NOTE: Setting of usb0 _may_ also control usb1 here. */ + chromeec_set_usb_charge_mode(slp_typ); + switch (slp_typ) { case ACPI_S3: - if (gnvs->s3u0 == 0) { - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - } - mainboard_disable_gpios(); /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); break; case ACPI_S5: - if (gnvs->s5u0 == 0) { - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - } - mainboard_disable_gpios(); /* Enable wake events */ |