diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-23 15:50:13 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2022-08-14 10:53:47 +0000 |
| commit | 29e71b1291bd22366d75b4dc3c897b355ff268ce (patch) | |
| tree | 21fe08ac0057cdbf839b0f8a2f9d440e834c6900 /src/mainboard/google/auron/variants | |
| parent | 2a90e396fc1b0d008024cff1a1b02ee8f1cd0036 (diff) | |
broadwell: Move some MRC/refcode settings to devicetree
There's no generic way to tell whether a mainboard has an EC or not.
Making Kconfig symbols for these options seems overkill, too. So, just
put them on the devicetree. Also, drop unnecessary assignments when the
board's current value is zero, as the struct defaults to zero already.
Change-Id: I8d3b352333bea7ea6f7b0f96d73e6c2d7d1a2cfb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55809
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/google/auron/variants')
8 files changed, 2 insertions, 13 deletions
diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c index b157fcdf80..866ea3a56c 100644 --- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 1; - /* P0: LTE */ pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); /* P1: POrt A, CN10 */ diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c index b157fcdf80..866ea3a56c 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c +++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 1; - /* P0: LTE */ pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); /* P1: POrt A, CN10 */ diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index ad8e50c4b6..75bf8ee20f 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -9,6 +9,8 @@ chip soc/intel/broadwell .backlight_pwm_hz = 200, }" + register "dq_pins_interleaved" = "true" + device cpu_cluster 0 on chip cpu/intel/haswell register "s0ix_enable" = "0" diff --git a/src/mainboard/google/auron/variants/buddy/pei_data.c b/src/mainboard/google/auron/variants/buddy/pei_data.c index fb9fc09a8c..e185d7ea79 100644 --- a/src/mainboard/google/auron/variants/buddy/pei_data.c +++ b/src/mainboard/google/auron/variants/buddy/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 1; - /* P0: Side USB3.0 port, USB3S1 */ pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0, USB_PORT_INTERNAL); /* P1: Rear USB3.0 port, USB3R1 */ diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c index 571aaafd33..78765148a6 100644 --- a/src/mainboard/google/auron/variants/buddy/spd/spd.c +++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c @@ -11,5 +11,4 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) pei_data->spd_addresses[2] = 0xa4; /* Enable 2x refresh mode */ pei_data->ddr_refresh_2x = 1; - pei_data->dq_pins_interleaved = 1; } diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c index b157fcdf80..866ea3a56c 100644 --- a/src/mainboard/google/auron/variants/gandof/pei_data.c +++ b/src/mainboard/google/auron/variants/gandof/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 1; - /* P0: LTE */ pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE); /* P1: POrt A, CN10 */ diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c index 663dd359e9..10862e8665 100644 --- a/src/mainboard/google/auron/variants/lulu/pei_data.c +++ b/src/mainboard/google/auron/variants/lulu/pei_data.c @@ -5,8 +5,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->ec_present = 1; - /* P0: Port B, CN01 (IOBoard) */ pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0, USB_PORT_BACK_PANEL); /* P1: Port A, CN01 */ diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c index 4ef45ee10c..b0d9803622 100644 --- a/src/mainboard/google/auron/variants/samus/pei_data.c +++ b/src/mainboard/google/auron/variants/samus/pei_data.c @@ -18,8 +18,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { 2, 0, 1, 3, 6, 4, 7, 5 }, { 2, 1, 0, 3, 6, 5, 4, 7 } }; - pei_data->ec_present = 1; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); |