mb/google/auron: Prepare devicetree for PCH split

Tested with BUILD_TIMELESS=1, all variants remain identical.

Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 72 insertions, 60 deletions

diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
index 60aef30a58..dc70085dd0 100644
--- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
@@ -7,9 +7,11 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_on_delay" = "70"	# 7ms
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
-	# DTLE DATA / EDGE values
-	register "sata_port0_gen3_dtle" = "0x5"
-	register "sata_port1_gen3_dtle" = "0x5"
-
-	device domain 0 on end
+	device domain 0 on
+#		chip soc/intel/broadwell/pch
+			# DTLE DATA / EDGE values
+			register "sata_port0_gen3_dtle" = "0x5"
+			register "sata_port1_gen3_dtle" = "0x5"
+#		end
+	end
 end
diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
index da80fecba8..b46e34cf83 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
@@ -7,9 +7,11 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_on_delay" = "2100"	# 210ms
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
-	# DTLE DATA / EDGE values
-	register "sata_port0_gen3_dtle" = "0x7"
-	register "sata_port1_gen3_dtle" = "0x5"
-
-	device domain 0 on end
+	device domain 0 on
+#		chip soc/intel/broadwell/pch
+			# DTLE DATA / EDGE values
+			register "sata_port0_gen3_dtle" = "0x7"
+			register "sata_port1_gen3_dtle" = "0x5"
+#		end
+	end
 end
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
index f14896425a..45229bad6d 100644
--- a/src/mainboard/google/auron/variants/buddy/overridetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -7,32 +7,34 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_on_delay" = "70"	# 7ms
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
-	register "sata_devslp_disable" = "0x1"
+	register "s0ix_enable" = "0"
 
-	register "sio_i2c0_voltage" = "1" # 1.8V
-	register "sio_i2c1_voltage" = "0" # 3.3V
+	device domain 0 on
+#		chip soc/intel/broadwell/pch
+			register "sata_devslp_disable" = "0x1"
 
-	# DTLE DATA / EDGE values
-	register "sata_port0_gen3_dtle" = "0x5"
-	register "sata_port1_gen3_dtle" = "0x5"
+			register "sio_i2c0_voltage" = "1" # 1.8V
+			register "sio_i2c1_voltage" = "0" # 3.3V
 
-	# Force enable ASPM for PCIe Port 5
-	register "pcie_port_force_aspm" = "0x10"
+			# DTLE DATA / EDGE values
+			register "sata_port0_gen3_dtle" = "0x5"
+			register "sata_port1_gen3_dtle" = "0x5"
 
-	# Enable port coalescing
-	register "pcie_port_coalesce" = "1"
+			# Force enable ASPM for PCIe Port 5
+			register "pcie_port_force_aspm" = "0x10"
 
-	# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
-	register "icc_clock_disable" = "0x01220000"
+			# Enable port coalescing
+			register "pcie_port_coalesce" = "1"
 
-	register "s0ix_enable" = "0"
+			# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
+			register "icc_clock_disable" = "0x01220000"
 
-	device domain 0 on
-		device pci 13.0 on  end # Smart Sound Audio DSP
-		device pci 1b.0 off end # High Definition Audio
-		device pci 1c.0 off end # PCIe Port #1
-		device pci 1c.2 on  end # PCIe Port #3 - LAN (becomes RP1)
-		device pci 1c.3 on  end # PCIe Port #4 - WLAN (becomes RP2)
-		device pci 1f.3 on  end # SMBus
+			device pci 13.0 on  end # Smart Sound Audio DSP
+			device pci 1b.0 off end # High Definition Audio
+			device pci 1c.0 off end # PCIe Port #1
+			device pci 1c.2 on  end # PCIe Port #3 - LAN (becomes RP1)
+			device pci 1c.3 on  end # PCIe Port #4 - WLAN (becomes RP2)
+			device pci 1f.3 on  end # SMBus
+#		end
 	end
 end
diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb
index 75c202d663..eae7999ea2 100644
--- a/src/mainboard/google/auron/variants/gandof/overridetree.cb
+++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb
@@ -7,9 +7,11 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_on_delay" = "500"	# 50ms
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
-	# DTLE DATA / EDGE values
-	register "sata_port0_gen3_dtle" = "0x5"
-	register "sata_port1_gen3_dtle" = "0x5"
-
-	device domain 0 on end
+	device domain 0 on
+#		chip soc/intel/broadwell/pch
+			# DTLE DATA / EDGE values
+			register "sata_port0_gen3_dtle" = "0x5"
+			register "sata_port1_gen3_dtle" = "0x5"
+#		end
+	end
 end
diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb
index 60aef30a58..dc70085dd0 100644
--- a/src/mainboard/google/auron/variants/lulu/overridetree.cb
+++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb
@@ -7,9 +7,11 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_on_delay" = "70"	# 7ms
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
-	# DTLE DATA / EDGE values
-	register "sata_port0_gen3_dtle" = "0x5"
-	register "sata_port1_gen3_dtle" = "0x5"
-
-	device domain 0 on end
+	device domain 0 on
+#		chip soc/intel/broadwell/pch
+			# DTLE DATA / EDGE values
+			register "sata_port0_gen3_dtle" = "0x5"
+			register "sata_port1_gen3_dtle" = "0x5"
+#		end
+	end
 end
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
index c5d27476c7..710fa95cac 100644
--- a/src/mainboard/google/auron/variants/samus/overridetree.cb
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -10,30 +10,32 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_on_delay" = "2000"	# 200ms
 	register "gpu_panel_power_backlight_off_delay" = "2000"	# 200ms
 
-	register "sata_port0_gen3_tx" = "0x72"
-
-	# Set I2C0 to 1.8V
-	register "sio_i2c0_voltage" = "1"
-
-	# Force enable ASPM for PCIe Port 3
-	register "pcie_port_force_aspm" = "0x04"
-	register "pcie_port_coalesce" = "1"
-
-	# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
-	register "icc_clock_disable" = "0x013b0000"
+	register "vr_slow_ramp_rate_set" = "3"
+	register "vr_slow_ramp_rate_enable" = "1"
 
 	# Disable S0ix for now
 	register "s0ix_enable" = "0"
 
-	register "vr_slow_ramp_rate_set" = "3"
-	register "vr_slow_ramp_rate_enable" = "1"
-
 	device domain 0 on
-		device pci 13.0 on  end # Smart Sound Audio DSP
-		device pci 15.3 on  end # GSPI0
-		device pci 1b.0 off end # High Definition Audio
-		device pci 1c.0 off end # PCIe Port #1
-		device pci 1c.2 on  end # PCIe Port #3
-		device pci 1d.0 off end # USB2 EHCI
+#		chip soc/intel/broadwell/pch
+			register "sata_port0_gen3_tx" = "0x72"
+
+			# Set I2C0 to 1.8V
+			register "sio_i2c0_voltage" = "1"
+
+			# Force enable ASPM for PCIe Port 3
+			register "pcie_port_force_aspm" = "0x04"
+			register "pcie_port_coalesce" = "1"
+
+			# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
+			register "icc_clock_disable" = "0x013b0000"
+
+			device pci 13.0 on  end # Smart Sound Audio DSP
+			device pci 15.3 on  end # GSPI0
+			device pci 1b.0 off end # High Definition Audio
+			device pci 1c.0 off end # PCIe Port #1
+			device pci 1c.2 on  end # PCIe Port #3
+			device pci 1d.0 off end # USB2 EHCI
+#		end
 	end
 end