diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-29 11:02:21 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-24 12:03:08 +0000 |
| commit | 739a6ad1ac098231c34587c69237906e721b7e91 (patch) | |
| tree | a8b30f1aa418b9bf8c6883e239f7aac718909816 /src/mainboard/google/auron/variants | |
| parent | d0b7a534ce798eff46a2de4857f48e65100c1572 (diff) | |
mb/google/auron: Use Haswell CPU code
The VR config and S0ix options are now specified for the CPU chip.
Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46945
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/auron/variants')
| -rw-r--r-- | src/mainboard/google/auron/variants/buddy/overridetree.cb | 9 | ||||
| -rw-r--r-- | src/mainboard/google/auron/variants/samus/overridetree.cb | 19 |
2 files changed, 22 insertions, 6 deletions
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 6762eb42c4..0570cdca55 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -9,7 +9,14 @@ chip soc/intel/broadwell .backlight_pwm_hz = 200, }" - register "s0ix_enable" = "0" + device cpu_cluster 0 on + chip cpu/intel/haswell + register "s0ix_enable" = "0" + + device lapic 0 on end + device lapic 0xacac off end + end + end device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 34a785b711..0a92efe70b 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -12,11 +12,20 @@ chip soc/intel/broadwell .backlight_pwm_hz = 200, }" - register "vr_slow_ramp_rate_set" = "3" - register "vr_slow_ramp_rate_enable" = "1" - - # Disable S0ix for now - register "s0ix_enable" = "0" + device cpu_cluster 0 on + chip cpu/intel/haswell + # Disable S0ix for now + register "s0ix_enable" = "0" + + register "vr_config" = "{ + .slow_ramp_rate_set = 3, + .slow_ramp_rate_enable = true, + }" + + device lapic 0 on end + device lapic 0xacac off end + end + end device domain 0 on chip soc/intel/broadwell/pch |