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| author | Matt DeVillier <matt.devillier@gmail.com> | 2020-03-30 13:21:45 -0500 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2020-04-03 16:21:55 +0000 |
| commit | ae01122b57eed272d6a10013b4686826dbfb95be (patch) | |
| tree | 46b35a3b2ae69e6deade1c3bd6b51f5ce4f78a49 /src/mainboard/google/auron/variants/samus/overridetree.cb | |
| parent | b54c5168bd1e82deee9f2bb0019490c167a66daf (diff) | |
mb/google/auron: Convert variants to use override devicetree
Since the variants' devicetrees are almost identical, convert to
using an overridetree setup for simplicity.
As part of the cleanup, drop unused PCIe RP5 for buddy as well.
Test: build all auron variants, compare generated static.c to ensure
resulting generated contents unchanged (although layout will)
Change-Id: I290e7243335a64afdcfc629db7b8ce18f5aa993c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/auron/variants/samus/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/auron/variants/samus/overridetree.cb | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb new file mode 100644 index 0000000000..93e96cac3f --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -0,0 +1,40 @@ +chip soc/intel/broadwell + + # Enable DDI2 Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "6" # 500ms + register "gpu_panel_power_up_delay" = "2000" # 200ms + register "gpu_panel_power_down_delay" = "500" # 50ms + register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms + register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms + + register "sata_port0_gen3_tx" = "0x72" + + # Set I2C0 to 1.8V + register "sio_i2c0_voltage" = "1" + + # Force enable ASPM for PCIe Port 3 + register "pcie_port_force_aspm" = "0x04" + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013b0000" + + # Disable S0ix for now + register "s0ix_enable" = "0" + + register "vr_slow_ramp_rate_set" = "3" + register "vr_slow_ramp_rate_enable" = "1" + + device domain 0 on + device pci 13.0 on end # Smart Sound Audio DSP + device pci 15.3 on end # GSPI0 + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 + device pci 1d.0 off end # USB2 EHCI + end +end |