Add/Combine Broadwell Chromebooks using variant board scheme

Combine existing boards google/auron_paine and google/samus with new
ChromeOS devices auron_yuna, gandof and lulu, using their common
reference board (auron) as a base.

Chromium sources used:
firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...]
firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...]
firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table]

Additionally, some minor cleanup/changes were made:
 - I2C devices set to use level (vs edge) interrupt triggering
 - HDA verb entries use simplified macro entry format
 - correct FADT table header version
 - remove unused ACPI device entries / .asl file(s)
 - clean up ACPI code (e.g., trackpad on Lulu)
 - adjust _CID for trackpad on Lulu in order to not load non-functional
    Windows driver (does not affect Linux)
 - remove unused header includes (multiple/various)
 - correct I2C addresses used for SMBIOS device entries
 - correct misc typos etc

The existing auron_paine samus boards are removed.

Variant setup modeled after google/slippy

Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

7 files changed, 520 insertions, 0 deletions

diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000000..40a4df051c
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl
@@ -0,0 +1,247 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#undef ENABLE_TOUCH_WAKE
+
+Scope (\_SB.PCI0.I2C0)
+{
+	Device (ATPA)
+	{
+		Name (_HID, "ATML0000")
+		Name (_DDN, "Atmel Touchpad")
+		Name (_UID, 2)
+		Name (_S0W, 4)
+		Name (ISTP, 1) /* Touchpad */
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				BOARD_TRACKPAD_I2C_ADDR,	// SlaveAddress
+				ControllerInitiated,		// SlaveMode
+				400000,				// ConnectionSpeed
+				AddressingMode7Bit,		// AddressingMode
+				"\\_SB.PCI0.I2C0",		// ResourceSource
+			)
+
+			// GPIO13 is PIRQL
+			Interrupt (ResourceConsumer, Level, ActiveLow) { 27 }
+		})
+
+		Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 3 })
+
+		Method (_DSW, 3, NotSerialized)
+		{
+			Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
+			If (LEqual (Arg0, 1)) {
+				// Enable GPIO as wake source
+				\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+			}
+		}
+
+		Method (_STA)
+		{
+			If (LEqual (\S1EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+	}
+
+	Device (CODC)
+	{
+		/*
+		 * TODO(kane): Need official HID.
+		 *
+		 */
+		Name (_HID, "RT5677CE")
+		Name (_DDN, "RT5667 Codec")
+		Name (_UID, 1)
+
+		Name (MB1, 1)   /* MICBIAS1 = 2.970V */
+		Name (DACR, 1)  /* Use codec internal 1.8V as DACREF source */
+		Name (DCLK, 0)  /* RT5677_DMIC_CLK1 */
+		Name (PCLK, 1)  /* RT5677_PDM_CLK_DIV2 (~3MHz) */
+		Name (IN1, 1)   /* IN1 differential */
+		Name (IN2, 0)   /* IN2 not differential */
+		Name (OUT1, 1)  /* LOUT1 differential */
+		Name (OUT2, 1)  /* LOUT2 differential */
+		Name (OUT3, 0)  /* LOUT3 differential */
+		Name (ASRC, 1)  /* Enable I2S1 ASRC */
+		Name (JD1, 0)   /* JackDetect1 is not used */
+		Name (JD2, 2)   /* Use GPIO5 as JackDetect2 */
+		Name (JD3, 3)   /* Use GPIO6 as JackDetect3 */
+
+		/* Add DT style bindings with _DSD */
+		Name (_DSD, Package () {
+			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+			Package () {
+				Package () { "realtek,micbias1", 1 },
+				Package () { "realtek,internal-dacref-en", 1 },
+				Package () { "realtek,in1-differential", 1 },
+				Package () { "realtek,in2-differential", 0 },
+				Package () { "realtek,lout1-differential", 1 },
+				Package () { "realtek,lout2-differential", 1 },
+				Package () { "realtek,lout3-differential", 0 },
+				Package () { "realtek,pdm_clk_div", 1 },
+				Package () { "realtek,dmic2_clk_pin", 0 },
+				Package () { "realtek,asrc-en", 1 },
+				Package () { "realtek,jd1-gpio", 0 },
+				Package () { "realtek,jd2-gpio", 2 },
+				Package () { "realtek,jd3-gpio", 3 },
+				Package () { "realtek,gpio-config",
+					Package () { 0, 0, 0, 0, 0, 2 } },
+			}
+		})
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				BOARD_CODEC_I2C_ADDR,		// SlaveAddress
+				ControllerInitiated,		// SlaveMode
+				400000,				// ConnectionSpeed
+				AddressingMode7Bit,		// AddressingMode
+				"\\_SB.PCI0.I2C0",		// ResourceSource
+			)
+
+			/* GPIO46 is PIRQO (use HOTWORD_DET as codec IRQ) */
+			Interrupt (ResourceConsumer, Edge, ActiveHigh) { 30 }
+
+			/*
+			 * Codec GPIOs are 1-based in the schematic
+			 *
+			 * [0] = Jack Detect (INPUT)
+			 * [1] = Mic Present (INPUT)
+			 * [2] = Interrupt to the host (OUTPUT)
+			 * [3] = Interrupt to the host (OUTPUT)
+			 * [4] = Headphone amp control (OUTPUT)
+			 */
+
+			/* Index 0:  Jack Detect - PLUG_DET is GPIO5 */
+			GpioIo (Exclusive, PullUp, , , IoRestrictionInputOnly,
+				"\\_SB.PCI0.I2C0.CODC") { 4 }
+
+			/* Index 1:  Mic Present - MIC_PRESENT_L is GPIO6 */
+			GpioIo (Exclusive, PullUp, , , IoRestrictionInputOnly,
+				"\\_SB.PCI0.I2C0.CODC") { 5 }
+
+			/* Index 2:  Codec IRQ - HOTWORD_DET_L is GPIO1 */
+			GpioIo (Exclusive, PullUp, , , IoRestrictionOutputOnly,
+				"\\_SB.PCI0.I2C0.CODC") { 0 }
+
+			/* Index 3:  Codec Wake - DSP_INT is GPIO4 */
+			GpioIo (Exclusive, PullUp, , , IoRestrictionOutputOnly,
+				"\\_SB.PCI0.I2C0.CODC") { 3 }
+
+			/* Index 4:  Headphone amp - HP_AMP_SHDN_L is GPIO2 */
+			GpioIo (Exclusive, PullDown, , , IoRestrictionOutputOnly,
+				"\\_SB.PCI0.I2C0.CODC") { 1 }
+		})
+
+		Name (_PRW, Package() { BOARD_CODEC_WAKE_GPIO, 3 })
+
+		Method (_DSW, 3, NotSerialized)
+		{
+			Store (BOARD_CODEC_WAKE_GPIO, Local0)
+			If (LEqual (Arg0, 1)) {
+				// Enable GPIO as wake source
+				\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+			}
+		}
+
+		Method (_STA)
+		{
+			If (LEqual (\S1EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+	}
+}
+
+Scope (\_SB.PCI0.I2C1)
+{
+	Device (ATSA)
+	{
+		Name (_HID, "ATML0001")
+		Name (_DDN, "Atmel Touchscreen")
+		Name (_UID, 5)
+		Name (_S0W, 4)
+		Name (ISTP, 0) /* TouchScreen */
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				BOARD_TOUCHSCREEN_I2C_ADDR,	// SlaveAddress
+				ControllerInitiated,		// SlaveMode
+				400000,				// ConnectionSpeed
+				AddressingMode7Bit,		// AddressingMode
+				"\\_SB.PCI0.I2C1",		// ResourceSource
+			)
+
+			// GPIO14 is PIRQM
+			Interrupt (ResourceConsumer, Level, ActiveLow) { 28 }
+		})
+
+#ifdef ENABLE_TOUCH_WAKE
+		Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 3 })
+
+		Method (_DSW, 3, NotSerialized)
+		{
+			Store (BOARD_CODEC_WAKE_GPIO, Local0)
+			If (LEqual (Arg0, 1)) {
+				// Enable GPIO as wake source
+				\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+			}
+		}
+#endif
+
+		Method (_STA)
+		{
+			If (LEqual (\S2EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+	}
+}
+
+Scope (\_SB.PCI0.SPI0)
+{
+	Device (CODC)
+	{
+		// TODO: Need official HID.
+		Name (_HID, "RT5677AA")
+		Name (_UID, 1)
+		Name (_CRS, ResourceTemplate ()
+		{
+			SpiSerialBus (
+				0,                   // DeviceSelection (CS0?)
+				PolarityLow,         // DeviceSelectionPolarity
+				FourWireMode,        // WireMode
+				8,                   // DataBitLength
+				ControllerInitiated, // SlaveMode
+				1000000,             // ConnectionSpeed (1MHz)
+				ClockPolarityLow,    // ClockPolarity
+				ClockPhaseFirst,     // ClockPhase
+				"\\_SB.PCI0.SPI0",   // ResourceSource
+				0,                   // ResourceSourceIndex
+				ResourceConsumer,    // ResourceUsage
+			)
+		})
+	}
+}
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/board_version.h b/src/mainboard/google/auron/variants/samus/include/variant/board_version.h
new file mode 100644
index 0000000000..f5371a19fa
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/board_version.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SAMUS_BOARD_VERSION_H
+#define SAMUS_BOARD_VERSION_H
+
+#define SAMUS_EC_BOARD_VERSION_EVT1	3
+#define SAMUS_EC_BOARD_VERSION_EVT2	4
+#define SAMUS_EC_BOARD_VERSION_EVT3	5
+#define SAMUS_EC_BOARD_VERSION_EVT4	0
+
+const char *samus_board_version(void);
+
+#endif
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/gpio.h b/src/mainboard/google/auron/variants/samus/include/variant/gpio.h
new file mode 100644
index 0000000000..8362a4dbfb
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/gpio.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SAMUS_GPIO_H
+#define SAMUS_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+	PCH_GPIO_UNUSED,        /* 0: UNUSED */
+	PCH_GPIO_UNUSED,        /* 1: UNUSED */
+	PCH_GPIO_UNUSED,        /* 2: UNUSED */
+	PCH_GPIO_UNUSED,        /* 3: UNUSED */
+	PCH_GPIO_NATIVE,        /* 4: NATIVE: I2C0_SDA_GPIO4 */
+	PCH_GPIO_NATIVE,        /* 5: NATIVE: I2C0_SCL_GPIO5 */
+	PCH_GPIO_NATIVE,        /* 6: NATIVE: I2C1_SDA_GPIO6 */
+	PCH_GPIO_NATIVE,        /* 7: NATIVE: I2C1_SCL_GPIO7 */
+	PCH_GPIO_ACPI_SCI,      /* 8: PCH_LTE_WAKE_L */
+	PCH_GPIO_INPUT_INVERT,  /* 9: TRACKPAD_INT_L (WAKE) */
+	PCH_GPIO_ACPI_SCI,      /* 10: PCH_WLAN_WAKE_L */
+	PCH_GPIO_UNUSED,        /* 11: UNUSED */
+	PCH_GPIO_UNUSED,        /* 12: UNUSED */
+	PCH_GPIO_PIRQ,          /* 13: TRACKPAD_INT_L (PIRQL) */
+	PCH_GPIO_PIRQ,          /* 14: TOUCH_INT_L (PIRQM) */
+	PCH_GPIO_UNUSED,        /* 15: UNUSED (STRAP) */
+	PCH_GPIO_INPUT,         /* 16: PCH_WP */
+	PCH_GPIO_UNUSED,        /* 17: UNUSED */
+	PCH_GPIO_UNUSED,        /* 18: UNUSED */
+	PCH_GPIO_UNUSED,        /* 19: UNUSED */
+	PCH_GPIO_NATIVE,        /* 20: PCIE_WLAN_CLKREQ_L */
+	PCH_GPIO_OUT_HIGH,      /* 21: PP3300_SSD_EN */
+	PCH_GPIO_UNUSED,        /* 22: UNUSED */
+	PCH_GPIO_OUT_LOW,       /* 23: PP3300_AUTOBAHN_EN */
+	PCH_GPIO_UNUSED,        /* 24: UNUSED */
+	PCH_GPIO_INPUT,         /* 25: EC_IN_RW */
+	PCH_GPIO_UNUSED,        /* 26: UNUSED */
+	PCH_GPIO_ACPI_SCI,      /* 27: PCH_WAKE_L */
+	PCH_GPIO_UNUSED,        /* 28: UNUSED */
+	PCH_GPIO_UNUSED,        /* 29: UNUSED */
+	PCH_GPIO_NATIVE,        /* 30: NATIVE: PCH_SUSWARN_L */
+	PCH_GPIO_NATIVE,        /* 31: NATIVE: ACOK_BUF */
+	PCH_GPIO_NATIVE,        /* 32: NATIVE: LPC_CLKRUN_L */
+	PCH_GPIO_NATIVE,        /* 33: NATIVE: SSD_DEVSLP */
+	PCH_GPIO_ACPI_SMI,      /* 34: EC_SMI_L */
+	PCH_GPIO_ACPI_SMI,      /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+	PCH_GPIO_ACPI_SCI,      /* 36: EC_SCI_L */
+	PCH_GPIO_UNUSED,        /* 37: UNUSED */
+	PCH_GPIO_UNUSED,        /* 38: UNUSED */
+	PCH_GPIO_UNUSED,        /* 39: UNUSED */
+	PCH_GPIO_NATIVE,        /* 40: NATIVE: PCH_USB1_OC_L */
+	PCH_GPIO_NATIVE,        /* 41: NATIVE: PCH_USB2_OC_L */
+	PCH_GPIO_UNUSED,        /* 42: WLAN_DISABLE_L */
+	PCH_GPIO_OUT_HIGH,      /* 43: PP1800_CODEC_EN */
+	PCH_GPIO_UNUSED,        /* 44: UNUSED */
+	PCH_GPIO_ACPI_SCI,      /* 45: DSP_INT - Codec Wake */
+	PCH_GPIO_PIRQ,          /* 46: HOTWORD_DET_L_3V3 (PIRQO) - Codec IRQ */
+	PCH_GPIO_OUT_LOW,       /* 47: SSD_RESET_L */
+	PCH_GPIO_UNUSED,        /* 48: UNUSED */
+	PCH_GPIO_UNUSED,        /* 49: UNUSED */
+	PCH_GPIO_UNUSED,        /* 50: UNUSED */
+	PCH_GPIO_UNUSED,        /* 51: UNUSED */
+	PCH_GPIO_INPUT,         /* 52: SIM_DET */
+	PCH_GPIO_UNUSED,        /* 53: UNUSED */
+	PCH_GPIO_UNUSED,        /* 54: UNUSED */
+	PCH_GPIO_UNUSED,        /* 55: UNUSED */
+	PCH_GPIO_UNUSED,        /* 56: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 57: CODEC_RESET_L */
+	PCH_GPIO_UNUSED,        /* 58: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 59: LTE_DISABLE_L */
+	PCH_GPIO_UNUSED,        /* 60: UNUSED */
+	PCH_GPIO_NATIVE,        /* 61: NATIVE: PCH_SUS_STAT */
+	PCH_GPIO_NATIVE,        /* 62: NATIVE: PCH_SUSCLK */
+	PCH_GPIO_NATIVE,        /* 63: NATIVE: PCH_SLP_S5_L */
+	PCH_GPIO_UNUSED,        /* 64: UNUSED */
+	PCH_GPIO_INPUT,         /* 65: RAM_ID3 */
+	PCH_GPIO_INPUT,         /* 66: RAM_ID3_OLD (STRAP) */
+	PCH_GPIO_INPUT,         /* 67: RAM_ID0 */
+	PCH_GPIO_INPUT,         /* 68: RAM_ID1 */
+	PCH_GPIO_INPUT,         /* 69: RAM_ID2 */
+	PCH_GPIO_UNUSED,        /* 70: UNUSED */
+	PCH_GPIO_NATIVE,        /* 71: NATIVE: MODPHY_EN */
+	PCH_GPIO_UNUSED,        /* 72: UNUSED */
+	PCH_GPIO_UNUSED,        /* 73: UNUSED */
+	PCH_GPIO_UNUSED,        /* 74: UNUSED */
+	PCH_GPIO_UNUSED,        /* 75: UNUSED */
+	PCH_GPIO_UNUSED,        /* 76: UNUSED */
+	PCH_GPIO_UNUSED,        /* 77: UNUSED */
+	PCH_GPIO_UNUSED,        /* 78: UNUSED */
+	PCH_GPIO_UNUSED,        /* 79: UNUSED */
+	PCH_GPIO_UNUSED,        /* 80: UNUSED */
+	PCH_GPIO_UNUSED,        /* 81: UNUSED */
+	PCH_GPIO_NATIVE,        /* 82: NATIVE: EC_RCIN_L */
+	PCH_GPIO_NATIVE,        /* 83: GSPI0_CS */
+	PCH_GPIO_NATIVE,        /* 84: GSPI0_CLK */
+	PCH_GPIO_NATIVE,        /* 85: GSPI0_MISO */
+	PCH_GPIO_NATIVE,        /* 86: GSPI0_MOSI (STRAP) */
+	PCH_GPIO_UNUSED,        /* 87: UNUSED */
+	PCH_GPIO_UNUSED,        /* 88: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 89: PP3300_SD_EN */
+	PCH_GPIO_UNUSED,        /* 90: UNUSED */
+	PCH_GPIO_UNUSED,        /* 91: UNUSED */
+	PCH_GPIO_UNUSED,        /* 92: UNUSED */
+	PCH_GPIO_UNUSED,        /* 93: UNUSED */
+	PCH_GPIO_UNUSED,        /* 94: UNUSED */
+	PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h
new file mode 100644
index 0000000000..5d088790a5
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[0] = {};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/onboard.h b/src/mainboard/google/auron/variants/samus/include/variant/onboard.h
new file mode 100644
index 0000000000..dcbfc6ed43
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/onboard.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#define BOARD_TRACKPAD_I2C_ADDR		0x4a
+#define BOARD_TOUCHSCREEN_I2C_ADDR	0x4b
+#define BOARD_CODEC_I2C_ADDR		0x2c
+
+#define BOARD_TRACKPAD_WAKE_GPIO	9	/* GPIO9 */
+#define BOARD_WLAN_WAKE_GPIO		10	/* GPIO10 */
+#define BOARD_TOUCHSCREEN_WAKE_GPIO	14	/* GPIO14 */
+#define BOARD_PP3300_AUTOBAHN_GPIO	23	/* GPIO23 */
+#define BOARD_WLAN_DISABLE_GPIO		42	/* GPIO42 */
+#define BOARD_CODEC_WAKE_GPIO		45	/* GPIO45 */
+#define BOARD_SSD_RESET_GPIO		47	/* GPIO47 */
+#define BOARD_LTE_DISABLE_GPIO		59	/* GPIO59 */
+
+#endif
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/spd.h b/src/mainboard/google/auron/variants/samus/include/variant/spd.h
new file mode 100644
index 0000000000..da48521a7e
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/spd.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN			256
+
+#define SPD_DRAM_TYPE		2
+#define SPD_DRAM_DDR3		0x0b
+#define SPD_DRAM_LPDDR3		0xf1
+#define SPD_DENSITY_BANKS	4
+#define SPD_ADDRESSING		5
+#define SPD_ORGANIZATION	7
+#define SPD_BUS_DEV_WIDTH	8
+#define SPD_PART_OFF		128
+#define SPD_PART_LEN		18
+
+/* Samus board memory configuration GPIOs */
+#define SPD_GPIO_BIT0		69
+#define SPD_GPIO_BIT1		68
+#define SPD_GPIO_BIT2		67
+#define SPD_GPIO_BIT3		65
+
+struct pei_data;
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif
diff --git a/src/mainboard/google/auron/variants/samus/include/variant/thermal.h b/src/mainboard/google/auron/variants/samus/include/variant/thermal.h
new file mode 100644
index 0000000000..8019f780ef
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/include/variant/thermal.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+/* Control TDP Settings */
+#define CTL_TDP_SENSOR_ID		0	/* PECI */
+#define CTL_TDP_POWER_LIMIT		12	/* 12W */
+#define CTL_TDP_THRESHILD_NORMAL	0	/*Normal TDP Threshold*/
+#define CTL_TDP_THRESHOLD_OFF		85	/* Normal at 85C */
+#define CTL_TDP_THRESHOLD_ON		90	/* Limited at 90C */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE		104
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE		95
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE			105
+
+#endif