diff options
author | Matt DeVillier <matt.devillier@gmail.com> | 2018-09-14 21:39:00 -0500 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-09-17 16:00:41 +0000 |
commit | 1b25f1b47c57e32f2a27480e12daa61331e456a3 (patch) | |
tree | 92b2f22a72f475155bd6f988ae3016e79e44b312 /src/mainboard/google/auron/variants/buddy/spd | |
parent | 99416035fac228f138f3e291a47173b66954b452 (diff) |
google/buddy: Add board as variant of google/auron
Add google/buddy (Acer Chromeboase 24) as a variant of google/auron,
with the following changes:
- add buddy-specific variant code
- add handling to auron for buddy's lan init, which no other variants have
- add handling to auron's mainboard ACPI due buddy having different PCIe
port assigments than all other variants
Ported from Chromium branch firmware-buddy-6301.202.B, commit
ebb82ce [Buddy: Lock management engine + SPI descriptor]
Test: build/boot Linux on google/buddy using SeaBIOS and Tianocore payloads
Change-Id: Ib76eef47677b72ddaef81a2decef189a5f20c20a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/auron/variants/buddy/spd')
-rw-r--r-- | src/mainboard/google/auron/variants/buddy/spd/Makefile.inc | 16 | ||||
-rw-r--r-- | src/mainboard/google/auron/variants/buddy/spd/spd.c | 32 |
2 files changed, 48 insertions, 0 deletions
diff --git a/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc b/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc new file mode 100644 index 0000000000..275d9836dd --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/spd/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd.c diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c new file mode 100644 index 0000000000..93e9fb2551 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/pei_data.h> +#include <variant/spd.h> + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *pei_data) +{ + pei_data->spd_addresses[0] = 0xa0; + pei_data->spd_addresses[1] = 0x00; + pei_data->spd_addresses[2] = 0xa4; + pei_data->spd_addresses[3] = 0x00; + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + /* Enable 2x refresh mode */ + pei_data->ddr_refresh_2x = 1; + pei_data->dq_pins_interleaved = 1; +} |