diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-23 20:39:17 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-27 10:05:35 +0000 |
| commit | 99af210456d346187692e0b7b982b01c28006ab0 (patch) | |
| tree | 6fc1fea67a0839f6ed714f859a8e4127ddf84a2c /src/mainboard/google/auron/variants/auron_yuna/overridetree.cb | |
| parent | ce19f4f8ad069bf1ba85578ffb416e2a1eb9f1c9 (diff) | |
mb/google/auron: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, all variants remain identical.
Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/auron/variants/auron_yuna/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/auron/variants/auron_yuna/overridetree.cb | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index da80fecba8..b46e34cf83 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -7,9 +7,11 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x7" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on +# chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x7" + register "sata_port1_gen3_dtle" = "0x5" +# end + end end |