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authorArthur Heymans <arthur@aheymans.xyz>2019-05-12 13:44:22 +0200
committerNico Huber <nico.h@gmx.de>2019-05-14 23:22:02 +0000
commitcadc70f7974db25144381b3ea26d4b660233f4dd (patch)
treede9e0677c328fe3d90389298c00f8831d0a6984d /src/mainboard/google/auron/romstage.c
parent57459dbeacb4759c3352206464b6c19b7add00d5 (diff)
soc/intel/broadwell: Move GPIO init to a common place
This also links the gpio configuration instead of including it as a header. Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/google/auron/romstage.c')
-rw-r--r--src/mainboard/google/auron/romstage.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c
index aea8e211fa..5e1a66ac24 100644
--- a/src/mainboard/google/auron/romstage.c
+++ b/src/mainboard/google/auron/romstage.c
@@ -17,11 +17,9 @@
#include <console/console.h>
#include <string.h>
#include <ec/google/chromeec/ec.h>
-#include <soc/gpio.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
-#include <variant/gpio.h>
#include <variant/spd.h>
#include "variant.h"
@@ -35,9 +33,6 @@ void mainboard_romstage_entry(struct romstage_params *rp)
post_code(0x32);
- /* Initialize GPIOs */
- init_gpios(mainboard_gpio_config);
-
/* Fill out PEI DATA */
memset(&pei_data, 0, sizeof(pei_data));
mainboard_fill_pei_data(&pei_data);