diff options
| author | Cliff Huang <cliff.huang@intel.com> | 2022-01-21 00:23:15 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-07 14:10:14 +0000 |
| commit | 4bc9ac7c292c806228c826b5971bf23c47b4f39f (patch) | |
| tree | 6e9556d8cb08657dda909bf2228e6f4cd815fa83 /src/mainboard/google/auron/mainboard.c | |
| parent | d5ae3f908af3c5201bd42fe411b32f97ac35ea4d (diff) | |
soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
Add L23 enter/exit, modPHY power gate, and source clock control methods.
DL23: method for L2/L3 entry.
L23D: method for L2/L3 exit.
PSD0: method for modPHY power gate.
SRCK: method for enabling/disable source clock.
These optional methods are to be used in the device ACPI to construct
flows with root port's power management functions.
Test:
Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/auron/mainboard.c')
0 files changed, 0 insertions, 0 deletions