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| author | Jason Chen <Jason-ch.Chen@mediatek.com> | 2023-03-23 14:59:34 +0800 |
|---|---|---|
| committer | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2023-04-10 01:55:31 +0000 |
| commit | 132a3ab1a71aa19a38eef9bb81f1b8e8ec437495 (patch) | |
| tree | 10bfed7c31ee2d12a954e892d683d0eabf4fbc44 /src/mainboard/google/auron/devicetree.cb | |
| parent | b7089e98e7d230d9e6be615f9d28397cc06119d2 (diff) | |
soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR
Set NOR pin drive to 8mA to comply with HW requirement.
This implementation is according to chapter 5.8 and 5.19 in MT8188
Functional Specification.
BUG=b:270911452
TEST=boot with following logs
[DEBUG] mtk_snfc_init: got pin drive: 0x3
[DEBUG] mtk_snfc_init: got pin drive: 0x3
[DEBUG] mtk_snfc_init: got pin drive: 0x3
[DEBUG] mtk_snfc_init: got pin drive: 0x3
Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74064
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/auron/devicetree.cb')
0 files changed, 0 insertions, 0 deletions