google/auron: Add mainboard

Add the Google Auron Broadwell Reference Mainboard. It is based
on the Google Peppy mainboard. It was merged from the following
chromium.org commit:  d20a1d1a22d64546a5d8761b18ab29732ec0b848

Change-Id: I716a79e198e91c428bd965fcd03665c2c7067602
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10500
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 74 insertions, 92 deletions

diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
index 505b39e0b9..77e71b8d3d 100644
--- a/src/mainboard/google/auron/devicetree.cb
+++ b/src/mainboard/google/auron/devicetree.cb
@@ -1,7 +1,4 @@
-chip northbridge/intel/haswell
-	# IGD Displays
-	register "gfx.ndid" = "3"
-	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+chip soc/intel/broadwell
 
 	# Enable eDP Hotplug with 6ms pulse
 	register "gpu_dp_d_hotplug" = "0x06"
@@ -24,103 +21,88 @@ chip northbridge/intel/haswell
 	register "gpu_panel_power_backlight_on_delay" = "2100"	# 210ms
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
-	device cpu_cluster 0 on
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-
-			register "c1_battery" = "2"	# ACPI(C1) = MWAIT(C1E)
-			register "c2_battery" = "3"	# ACPI(C2) = MWAIT(C3)
-			register "c3_battery" = "9"	# ACPI(C3) = MWAIT(C7S)
-
-			register "c1_acpower" = "2"	# ACPI(C1) = MWAIT(C1E)
-			register "c2_acpower" = "3"	# ACPI(C2) = MWAIT(C3)
-			register "c3_acpower" = "9"	# ACPI(C3) = MWAIT(C7S)
-		end
-	end
+	register "pirqa_routing" = "0x8b"
+	register "pirqb_routing" = "0x8a"
+	register "pirqc_routing" = "0x8b"
+	register "pirqd_routing" = "0x8b"
+	register "pirqe_routing" = "0x80"
+	register "pirqf_routing" = "0x80"
+	register "pirqg_routing" = "0x80"
+	register "pirqh_routing" = "0x80"
 
-	device domain 0 on
-		device pci 00.0 on end # host bridge
-		device pci 02.0 on end # vga controller
-		device pci 03.0 on end # mini-hd audio
+	# EC range is 0x800-0x9ff
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x00fc0901"
 
-		chip southbridge/intel/lynxpoint
-			register "pirqa_routing" = "0x8b"
-			register "pirqb_routing" = "0x8a"
-			register "pirqc_routing" = "0x8b"
-			register "pirqd_routing" = "0x8b"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x80"
+	# EC_SMI is GPIO34
+	register "alt_gp_smi_en" = "0x0004"
+	register "gpe0_en_1" = "0x00000000"
+	# EC_SCI is GPIO36
+	register "gpe0_en_2" = "0x00000010"
+	register "gpe0_en_3" = "0x00000000"
+	register "gpe0_en_4" = "0x00000000"
 
-			# EC range is 0x800-0x9ff
-			register "gen1_dec" = "0x00fc0801"
-			register "gen2_dec" = "0x00fc0901"
+	register "sata_port_map" = "0x1"
+	register "sio_acpi_mode" = "1"
 
-			# EC_SMI is GPIO34
-			register "alt_gp_smi_en" = "0x0004"
-			register "gpe0_en_1" = "0x00000000"
-			# EC_SCI is GPIO36
-			register "gpe0_en_2" = "0x00000010"
-			register "gpe0_en_3" = "0x00000000"
-			register "gpe0_en_4" = "0x00000000"
+	# DTLE DATA / EDGE values
+	register "sata_port0_gen3_dtle" = "0x5"
+	register "sata_port1_gen3_dtle" = "0x5"
 
-			register "ide_legacy_combined" = "0x0"
-			register "sata_ahci" = "0x1"
-			register "sata_port_map" = "0x1"
+	# Force enable ASPM for PCIe Port1
+	register "pcie_port_force_aspm" = "0x01"
 
-			# DTLE DATA / EDGE values
-			register "sata_port0_gen3_dtle" = "0x5"
-			register "sata_port1_gen3_dtle" = "0x5"
+	# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
+	register "icc_clock_disable" = "0x013c0000"
 
-			register "sio_acpi_mode" = "0"
-			register "sio_i2c0_voltage" = "0" # 3.3V
-			register "sio_i2c1_voltage" = "0" # 3.3V
+	register "s0ix_enable" = "1"
 
-			# Force enable ASPM for PCIe Port1
-			register "pcie_port_force_aspm" = "0x01"
-
-			# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
-			register "icc_clock_disable" = "0x013c0000"
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
 
-			device pci 13.0 off end # Smart Sound Audio DSP
-			device pci 14.0 on end # USB3 XHCI
-			device pci 15.0 on end # Serial I/O DMA
-			device pci 15.1 on end # I2C0
-			device pci 15.2 on end # I2C1
-			device pci 15.3 off end # GSPI0
-			device pci 15.4 off end # GSPI1
-			device pci 15.5 off end # UART0
-			device pci 15.6 off end # UART1
-			device pci 16.0 on end # Management Engine Interface 1
-			device pci 16.1 off end # Management Engine Interface 2
-			device pci 16.2 off end # Management Engine IDE-R
-			device pci 16.3 off end # Management Engine KT
-			device pci 17.0 off end # SDIO
-			device pci 19.0 off end # GbE
-			device pci 1b.0 on end # High Definition Audio
-			device pci 1c.0 on end # PCIe Port #1
-			device pci 1c.1 off end # PCIe Port #2
-			device pci 1c.2 off end # PCIe Port #3
-			device pci 1c.3 off end # PCIe Port #4
-			device pci 1c.4 off end # PCIe Port #5
-			device pci 1c.5 off end # PCIe Port #6
-			device pci 1d.0 on end # USB2 EHCI
-			device pci 1e.0 off end # PCI bridge
-			device pci 1f.0 on
-				chip ec/google/chromeec
-					# We only have one init function that
-					# we need to call to initialize the
-					# keyboard part of the EC.
-					device pnp ff.1 on # dummy address
-					end
+	device domain 0 on
+		device pci 00.0 on end # host bridge
+		device pci 02.0 on end # vga controller
+		device pci 03.0 on end # mini-hd audio
+		device pci 13.0 off end # Smart Sound Audio DSP
+		device pci 14.0 on end # USB3 XHCI
+		device pci 15.0 on end # Serial I/O DMA
+		device pci 15.1 on end # I2C0
+		device pci 15.2 on end # I2C1
+		device pci 15.3 off end # GSPI0
+		device pci 15.4 off end # GSPI1
+		device pci 15.5 off end # UART0
+		device pci 15.6 off end # UART1
+		device pci 16.0 on end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT
+		device pci 17.0 off end # SDIO
+		device pci 19.0 off end # GbE
+		device pci 1b.0 on end # High Definition Audio
+		device pci 1c.0 on end # PCIe Port #1
+		device pci 1c.1 off end # PCIe Port #2
+		device pci 1c.2 off end # PCIe Port #3
+		device pci 1c.3 off end # PCIe Port #4
+		device pci 1c.4 off end # PCIe Port #5
+		device pci 1c.5 off end # PCIe Port #6
+		device pci 1d.0 on end # USB2 EHCI
+		device pci 1e.0 off end # PCI bridge
+		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				# Rising edge interrupt
+				register "irq_polarity" = "2"
+				device pnp 0c31.0 on
+					irq 0x70 = 10
 				end
-			end # LPC bridge
-			device pci 1f.2 on end # SATA Controller
-			device pci 1f.3 on end # SMBus
-			device pci 1f.6 on end # Thermal
-		end
+			end
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end # LPC bridge
+		device pci 1f.2 on end # SATA Controller
+		device pci 1f.3 off end # SMBus
+		device pci 1f.6 on end # Thermal
 	end
 end