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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-06-17 00:38:20 +0530 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-06-25 13:43:01 +0000 |
| commit | e40b9481e616f8b8a899ac9bb9fbf1cda20d7114 (patch) | |
| tree | 2affa524a52a7c4b3edf8cf9c0469f4e3139720f /src/mainboard/google/auron/chromeos.c | |
| parent | d95dba0ce34df0a0b61e70fa89470ab113e2e918 (diff) | |
soc/intel/cannonlake: Add PchPmPwrCycDur to chip options
Add PchPmPwrCycDur to chip options to control the UPD FSPS PchPmPwrCycDur
from devicetree. The UPD determines the minimum time a platform will stay
in reset during host partition reset with power cycle or global reset.
This patch also ensures configured PchPmPwrCycDur value doesn't violate
the PCH EDS specification.
TEST=Verified on Hatch and Puff boards
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I55e836c78fab34e34d57b04428a1498b7dc7174b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'src/mainboard/google/auron/chromeos.c')
0 files changed, 0 insertions, 0 deletions