diff options
| author | Hung-Te Lin <hungte@chromium.org> | 2020-05-26 23:49:21 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-10-22 02:13:43 +0000 |
| commit | c47ed6e8c3106b243f6c1df23d21785bdf61bd10 (patch) | |
| tree | 5cd983bdc2bc1d67e6fa1855136e4653c34e17a9 /src/mainboard/google/asurada/bootblock.c | |
| parent | 5ed4d63fe12b9dc744a15a76c136132cc42308db (diff) | |
mb/google/asurada: Add Chrome OS GPIOs
Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs.
BUG=None
TEST=emerge-asurada coreboot; # also boots into emmc
BRANCH=None
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46386
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/asurada/bootblock.c')
| -rw-r--r-- | src/mainboard/google/asurada/bootblock.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index cce14381f6..04e8898d85 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -3,8 +3,12 @@ #include <bootblock_common.h> #include <soc/spi.h> +#include "gpio.h" + void bootblock_mainboard_init(void) { mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + setup_chromeos_gpios(); + gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING); } |