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authorStefan Reinauer <reinauer@chromium.org>2015-07-30 16:17:10 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-10-30 18:13:53 +0100
commit273911cfd6c729406844aa00c0274fefff2d0919 (patch)
treeb4072859769a52516bfd3d8c83d49e4a97461612 /src/mainboard/gizmosphere
parent5c5c4a694314d9b2a6d085fb97770d0ee12cc17c (diff)
mainboard 64bit fixes
Change-Id: I2b4338927d56a2075c0a95f2ab981f1beaf69cc7 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11082 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/gizmosphere')
-rw-r--r--src/mainboard/gizmosphere/gizmo/mainboard.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c
index d04a0aaca2..866806cbad 100644
--- a/src/mainboard/gizmosphere/gizmo/mainboard.c
+++ b/src/mainboard/gizmosphere/gizmo/mainboard.c
@@ -75,17 +75,16 @@ static void mainboard_enable(device_t dev)
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
}
-void mainboard_final( void *chip_info );
-void mainboard_final( void *chip_info )
+static void mainboard_final(void *chip_info)
{
device_t ahci_dev;
- u32 ABAR;
+ uintptr_t ABAR;
u8 *memptr;
ahci_dev = dev_find_slot(0, PCI_DEVFN(0x11, 0));
ABAR = pci_read_config32(ahci_dev, 0x24);
ABAR &= 0xFFFFFC00;
- memptr = (u8 *) (ABAR + 0x100 + 0x80 + 0x2C); /* we're on the 2nd port */
+ memptr = (u8 *)(ABAR + 0x100 + 0x80 + 0x2C); /* we're on the 2nd port */
*memptr = 0x21; /* force to GEN2 and start re-negotiate */
mdelay (1);
*memptr = 0x20;