diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2017-05-04 19:00:33 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2017-05-21 16:38:34 +0200 |
| commit | ac27d3688a862074631e3a1390caf85c068d55cb (patch) | |
| tree | 904158a0566038c8d2c51972e2318370ef5617b2 /src/mainboard/gigabyte | |
| parent | 7565cf1a49bf9688e636e1ebc6a4cb8e1e567e1b (diff) | |
mb/*/romstage: Don't lock ETR3 CF9GR in early romstage
Do not lock ETR3 CF9GR in early romstage.
As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done
in bd82x6x's finalize handler.
Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/gigabyte')
| -rw-r--r-- | src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index bb3b223c3b..cbc55921a8 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -153,7 +153,7 @@ void pch_enable_lpc(void) pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index 4a02790c39..22a10aef4d 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -85,7 +85,7 @@ void pch_enable_lpc(void) pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |