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authorRonald G. Minnich <rminnich@gmail.com>2016-12-19 09:06:00 -0800
committerRonald G. Minnich <rminnich@gmail.com>2016-12-20 00:10:33 +0100
commitf171e6645df0ed9bc214b408eca7e8fdc7c04075 (patch)
tree327f5baf4293be803278cf0cd6ea9597428e854a /src/mainboard/gigabyte
parent41f669023953b3d032078ffc17d80944880d1db7 (diff)
riscv: enable counters via m[us]counteren
The user and supervisor counters could not be safely enabled before as the register numbers were not finalized. Now that everyone agrees, we can enable them. Until we are sure the toolchains are caught up, we use the hardcode name with the register names in comments. As soon as toolchains settle down we'll do one more pass and convert to the symbolic names. Tested on lowrisc bitstream and SPIKE simulator. Change-Id: I21fe5cac44fafe4b7806e004c179aa27541be4b6 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17920 Tested-by: build bot (Jenkins) Reviewed-by: Alex Bradbury <asb@lowrisc.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Andrew Waterman <aswaterman@gmail.com>
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