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authorUwe Hermann <uwe@hermann-uwe.de>2010-11-21 22:47:22 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-21 22:47:22 +0000
commit7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32 (patch)
tree5339d014fbd29d3eb27cc82987eb7d655d9d8d1a /src/mainboard/gigabyte
parent57b2ff886e0ce2c92820f5722c8031def3ac94cf (diff)
Simplify a few code chunks, fix whitespace and indentation.
Also, remove some less useful comments, some dead code / unused functions. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/romstage.c36
-rw-r--r--src/mainboard/gigabyte/m57sli/romstage.c39
-rw-r--r--src/mainboard/gigabyte/ma785gmt/romstage.c20
-rw-r--r--src/mainboard/gigabyte/ma78gm/romstage.c20
4 files changed, 32 insertions, 83 deletions
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 70e3f96cca..4b31b545af 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -56,14 +56,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -119,35 +113,29 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the sis966 */
sis966_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x23, 0);
@@ -194,21 +182,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index c9599094ab..968e384021 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -53,14 +53,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -111,17 +105,16 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
uint8_t tmp = 0;
@@ -129,18 +122,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
/* The following line will set CLKIN to 24 MHz, external */
@@ -153,9 +141,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Set Serial Flash interface to 0x0820 */
pnp_write_config(GPIO_DEV, 0x64, 0x08);
pnp_write_config(GPIO_DEV, 0x65, 0x20);
- /* We can get away with not resetting the logical device because
- * it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE) will do that.
- */
}
it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
@@ -200,21 +185,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index b784474ff9..7b7f239d0e 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -48,15 +48,11 @@ static int smbus_read_byte(u32 device, u32 address);
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -76,8 +72,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@ -86,7 +81,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
@@ -153,13 +147,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
- #endif
+#endif
post_code(0x38);
@@ -167,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb700_early_setup();
- #if CONFIG_SET_FIDVID
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@ -188,7 +182,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
- #endif
+#endif
rs780_htinit();
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 116229605e..9a753b9201 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -52,15 +52,11 @@ static int smbus_read_byte(u32 device, u32 address);
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -80,8 +76,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@ -90,7 +85,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
@@ -155,13 +149,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
- #endif
+#endif
post_code(0x38);
@@ -169,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb700_early_setup();
- #if CONFIG_SET_FIDVID
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@ -190,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
- #endif
+#endif
rs780_htinit();