diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-16 14:02:25 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-18 19:03:22 +0000 |
| commit | 157b189f6b97b6e9ecd8d29edbbd045fbbc231f5 (patch) | |
| tree | 4562bd212e40d0832fa893935d85a06d82f8a897 /src/mainboard/gigabyte | |
| parent | 146c09823333c52e8bbca98465ccc8512ec1daa2 (diff) | |
cpu/intel: Enter romstage without BIST
When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.
Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/gigabyte')
| -rw-r--r-- | src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c | 10 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 4 |
2 files changed, 3 insertions, 11 deletions
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index bdb0a38eab..7a2b38499b 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -21,7 +21,6 @@ #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -135,12 +134,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0; - - if (bist == 0) - enable_lapic(); + enable_lapic(); ich7_enable_lpc(); /* Enable SuperIO PM */ @@ -153,9 +150,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index e20fb7a888..c13d4d6419 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -22,7 +22,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> @@ -122,7 +121,7 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -139,7 +138,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); |