diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-11-29 17:36:51 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-02 14:39:56 +0000 |
| commit | dc3beea75d3050600842112cfd7fd48baa65278d (patch) | |
| tree | ca9839a61c90cc7b972650c0eb1a2e92a6a25eb9 /src/mainboard/gigabyte | |
| parent | 87a98b55b2466638587ea44fc7eaa13d93525656 (diff) | |
sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}
Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/gigabyte')
| -rw-r--r-- | src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 28af26fe97..673172dd5e 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -61,8 +61,8 @@ chip northbridge/intel/i945 register "gpe0_en" = "0" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index d2168630ba..3a4ae45cda 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -32,8 +32,8 @@ chip northbridge/intel/x4x # Northbridge register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x40" |