mainboard/*/*/mptable.c: Improve code formatting

Change-Id: I341293cd334d6d465636db7e81400230d61bc693
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16723
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

2 files changed, 58 insertions, 58 deletions

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index a7962f542d..15442057f5 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -30,15 +30,15 @@ extern unsigned apicid_sis966;
 
 static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
 	unsigned sbdn;
 	int i, j, bus_isa;
 
-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);
 
-        smp_write_processors(mc);
+	smp_write_processors(mc);
 
 	get_bus_conf();
 	sbdn = sysconf.sbdn;
@@ -46,13 +46,13 @@ static void *smp_write_config_table(void *v)
 	mptable_write_buses(mc, NULL, &bus_isa);
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
-        {
-                device_t dev;
+	{
+		device_t dev;
 		struct resource *res;
 		uint32_t dword;
 
-                dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0));
-                if (dev) {
+		dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0));
+		if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_1);
 			if (res) {
 				smp_write_ioapic(mc, apicid_sis966, 0x11,
@@ -60,15 +60,15 @@ static void *smp_write_config_table(void *v)
 			}
 
 			dword = 0x43c6c643;
-	        	pci_write_config32(dev, 0x7c, dword);
+			pci_write_config32(dev, 0x7c, dword);
 
-		        dword = 0x81001a00;
-		        pci_write_config32(dev, 0x80, dword);
+			dword = 0x81001a00;
+			pci_write_config32(dev, 0x80, dword);
 
-	        	dword = 0xd0001202;
-		        pci_write_config32(dev, 0x84, dword);
+			dword = 0xd0001202;
+			pci_write_config32(dev, 0x84, dword);
 
-                }
+		}
 	}
 
 	mptable_add_isa_interrupts(mc, bus_isa, apicid_sis966, 0);
@@ -77,28 +77,28 @@ static void *smp_write_config_table(void *v)
  * associated with a specific bus/device/function tuple.
  */
 #define PCI_INT(bus, dev, fn, pin)					\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin))
 
-        PCI_INT(0, sbdn+1, 1, 0xa);
-        PCI_INT(0, sbdn+2, 0, 0x16); // 22
-        PCI_INT(0, sbdn+2, 1, 0x17); // 23
-        PCI_INT(0, sbdn+6, 1, 0x17); // 23
-        PCI_INT(0, sbdn+5, 0, 0x14); // 20
-        PCI_INT(0, sbdn+5, 1, 0x17); // 23
-        PCI_INT(0, sbdn+5, 2, 0x15); // 21
-        PCI_INT(0, sbdn+8, 0, 0x16); // 22
+	PCI_INT(0, sbdn+1, 1, 0xa);
+	PCI_INT(0, sbdn+2, 0, 0x16); // 22
+	PCI_INT(0, sbdn+2, 1, 0x17); // 23
+	PCI_INT(0, sbdn+6, 1, 0x17); // 23
+	PCI_INT(0, sbdn+5, 0, 0x14); // 20
+	PCI_INT(0, sbdn+5, 1, 0x17); // 23
+	PCI_INT(0, sbdn+5, 2, 0x15); // 21
+	PCI_INT(0, sbdn+8, 0, 0x16); // 22
 
 	for(j = 7; j >= 2; j--) {
 		if(!bus_sis966[j]) continue;
-	        for(i = 0; i < 4; i++) {
-        	        PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4);
-        	}
+		for(i = 0; i < 4; i++) {
+			PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4);
+		}
 	}
 
 	for(j = 0; j < 2; j++)
-	        for(i = 0; i < 4; i++) {
-        	        PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4);
-	        }
+		for(i = 0; i < 4; i++) {
+			PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4);
+		}
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
 	mptable_lintsrc(mc, bus_isa);
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 403b96952c..019a7f5eab 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -29,15 +29,15 @@ extern unsigned apicid_mcp55;
 
 static void *smp_write_config_table(void *v)
 {
-        struct mp_config_table *mc;
+	struct mp_config_table *mc;
 	unsigned sbdn;
 	int i, j, k, bus_isa;
 
-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);
 
-        smp_write_processors(mc);
+	smp_write_processors(mc);
 
 	get_bus_conf();
 	sbdn = sysconf.sbdn;
@@ -45,22 +45,22 @@ static void *smp_write_config_table(void *v)
 	mptable_write_buses(mc, NULL, &bus_isa);
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
-        {
-                device_t dev;
+	{
+		device_t dev;
 		struct resource *res;
 
-                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
-                if (dev) {
+		dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+		if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_1);
 			if (res) {
 				smp_write_ioapic(mc, apicid_mcp55, 0x11,
 						 res2mmio(res, 0, 0));
 			}
 			/* set up the interrupt registers of mcp55 */
-	        	pci_write_config32(dev, 0x7c, 0xc643c643);
-		        pci_write_config32(dev, 0x80, 0x8da01009);
-		        pci_write_config32(dev, 0x84, 0x200018d2);
-                }
+			pci_write_config32(dev, 0x7c, 0xc643c643);
+			pci_write_config32(dev, 0x80, 0x8da01009);
+			pci_write_config32(dev, 0x84, 0x200018d2);
+		}
 	}
 
 	mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
@@ -83,28 +83,28 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */
 
 	/* The PCIe slots, each on its own bus */
-        k = 1;
-        for(i = 0; i < 4; i++){
-                for(j = 7; j > 1; j--){
-                        if(k > 3) k = 0;
-                        PCI_INT(j,0,i, 16+k);
-                        k++;
-                }
-                k--;
-        }
+	k = 1;
+	for(i = 0; i < 4; i++){
+		for(j = 7; j > 1; j--){
+			if(k > 3) k = 0;
+			PCI_INT(j,0,i, 16+k);
+			k++;
+		}
+		k--;
+	}
 
 	/* On bus 1: the PCI bus slots...
-	   physical PCI slots are j = 7,8
-	   FireWire is j = 10
+	 * physical PCI slots are j = 7,8
+	 * FireWire is j = 10
 	*/
-        k = 2;
-        for(i = 0; i < 4; i++){
-                for(j = 6; j < 11; j++){
-                        if(k > 3) k = 0;
-                        PCI_INT(1,j,i, 16+k);
-                        k++;
-                }
-        }
+	k = 2;
+	for(i = 0; i < 4; i++){
+		for(j = 6; j < 11; j++){
+			if(k > 3) k = 0;
+			PCI_INT(1,j,i, 16+k);
+			k++;
+		}
+	}
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
 	mptable_lintsrc(mc, bus_isa);